KR910008418B1 - Bus arbitration circuit in round-robin selecting method - Google Patents

Abstract

A bus arbitration circuit features incorporating bus masters with same priorities for VME bus system, while there was performance degradation caused by bus grant delayed up to 4-olock period upon bus request signal. Thus it minimizes bus arbitration time and its error. The system consists of multiplexer (10) for bus request input, choosing output and interrupting other request, control signal generator (20) for the first and second control signal, counter (30) for data count, decoder (40) to decode counter output and to give selecting signal, the first-fourth bus arbiter (50-80) and gates (91-94) to generate corresponding bus grant signal to request signal by logic combination.

Description

Round-Robin Selective Bus Arbitration Circuit

1 is a conventional bus arbitration circuit diagram.

2 is a block diagram according to the present invention.

3 is a concrete circuit diagram of state 1 of FIG. 2.

4 is a timing diagram illustrating an example of bus arbitration.

* Explanation of symbols for main parts of the drawings

10: multiplexer 20: clock generator

30: counter 40: decoder

50-80: Bus Arbitration Unit 90-94: Output Gate

The present invention relates to a bus arbitration circuit of a system using a VME bus, and more particularly, to a bus arbitration circuit of a round robin selection method in which multiple bus masters can have bus arbitration with the same priority.

라 칭함)가 디액티브(deactive)될 때까지 유지한다. 즉 버스승인신호를 받은 버스마스터가 버스의 억세스를 완료하면, 홀드신호를 디스에이블시켜 다시 카운터(1)가 동작하도록 한다. 상기와 같은 동작을 반복하여 마스터의 버스요구신호를 중재하게 된다. 그러나 상기와 같은 방법은 버스요구신호가 엑티브된 후 버스승인신호를 받을 때까지의 시간(bus arbitration time)이 길어지게 된다. 즉 카운터의 값이 "00"일때에는 버스요구신호

만이 승인되므로, 이 상태에서 버스요구신호

가 액티브되면 카운터의 값이 "11"이 될 때까지 버스승인신호

가 액티브되지 못한다. 이로 인하여 버스요구신호 발생후 버스승인신호가 발생되는 시간이 최대 4클럭 주기동안 지연되므로 VME 버스시스템의 성능을 저하시켰던 문제점이 있었다.1 is a conventional bus arbiter, which applies a system clock (SYSCLK) to the counter (1) to mediate _a bus request signal (BR ₃ -BR _a ) from the VME bus master. do. The counter 1 then sets the system clock SYSCLK to 00 → 10 → 10 → 11 → 00... Count in order of. At this time, the bus arbitration unit 3 generates a bus request signal output from the latch 2 as a bus grant signal according to the output of the counter 1, and holds the counter 1 in that state. hold). Bus busy signal after

And until it becomes deactive. That is, when the bus master receiving the bus acknowledgment signal completes access to the bus, the hold signal is disabled to allow the counter 1 to operate again. The above operation is repeated to mediate the bus request signal of the master. However, in the above method, the bus arbitration time after the bus request signal is activated becomes long. That is, when the counter value is "00", the bus request signal

Only bus is approved, so the bus request signal in this state

Is activated, the bus acknowledgment signal until the counter value is "11".

Is not active. As a result, the time required for generating the bus acknowledgment signal after the bus request signal is delayed for a maximum of 4 clock cycles causes a problem of degrading the performance of the VME bus system.

It is therefore an object of the present invention to provide a circuit that can arbitrate each bus master to use the bus with the same priority in a VME bus system.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of the present invention, and inputs a bus request signal of each bus master applied to the first terminal when the second control signal is generated, and selects an output applied to the second terminal when the first control signal is generated, thereby selecting another bus. A multiplexer 10 for blocking generation of a request signal, a control signal generator 20 for generating the first control signal when the bus request signal is generated, and a second control signal for generating a bus use signal, and using the bus A counter 30 which is operated when the signal is released and sequentially outputs count data for giving priority to the signal; and decoding the output of the counter 30 to generate a selection signal for a corresponding counter value among the first to fourth selection signals. The decoder 40 and the bus request signal have priority in different states, and the bus arbitration unit is enabled by the output of the decoder 40 so that the corresponding bus arbitration unit is enabled. The bus acknowledgment signal for the first and fourth bus arbitration units 50-80 and the bus acknowledgment signals of the first and fourth bus arbitration units 50-80, which are generated according to their own priorities, are logically combined. Gates 91-94 for generating a bus acknowledgment signal for the bus request signal.

FIG. 3 is a detailed circuit diagram of the first arbitration unit 50 in the second diagram. When the counter 30 outputs "00", the decoder 40 generates the first selection signal so that BR ₃ ^* → BR ₂ ^* → Generates bus acknowledgment signal in the bus request order of BR ₁ ^* → BR ₀ ^* .

가

보다 우선권을 갖는 버스중재부에서 제4a도는

와

신호가 동시에 액티브된 경우

에 대한 버스승인신호

가 먼저 발생하는 과정을 도시하고 있고, 제4b도는

이 먼저 액티브된 후

가 액티브된 경우

이 먼저 발생한 후

가 발생됨을 도시하고 있다.4 is a timing diagram of a bus arbitration circuit according to the present invention.

end

In the more preferred bus arbitration department, Figure 4a

Wow

If the signals are active at the same time

Bus approval signal for

Shows the process that occurs first, and FIG.

After this first becomes active

Is active

After this happens first

Shows that is generated.

Based on the above configuration, the present invention will be described in detail with reference to FIGS.

First, the counter 30 is a quaternary up counter which performs a function for selecting the first to fourth bus arbitration units 50-80 having priority for different bus request signals, and the decoder 40. ) Generates a selection signal according to the output of the counter 30 to enable the corresponding bus arbitration unit.

Here, it is assumed that the bus arbitration priority of the first-fourth bus quintet 50-80 is as shown in Table 1 below.

TABLE 1

신호가 액티브(low) 상태에서는 카운터(30)가 리세트 상태가 되므로 "00"이 된다. 이 상태는 카운터(30)의 초기상태가 된다.Initial system reset

When the signal is in the low state, the counter 30 becomes the reset state, and thus becomes " 00 ". This state becomes the initial state of the counter 30.

When the determination is made as described above, the decoder 40 generates the first selection signal, and the first bus arbitration unit 50 is enabled due to the in. At this time, the remaining bus arbitration units 60, 70, and 80 are in a disabled state. Therefore, the priority of bus arbitration is BR ₃ ^* , as shown in Table 1 above, and BR ^* → BR ₁ ^* → BR ₀ ^* .

)를 액티브(low)시킬때까지 유지된다.In the above state, if an arbitrary bus request signal is generated through the first terminal A of the multiplexer 10, the bus acknowledgment signal is determined according to the priority order of the first bus arbitrator 50, and the control signal generator ( 20 generates a first control signal of a "low" state generated according to the state of the bus request signal to convert the input of the multiplexer 10 to the second terminal (A) side. Therefore, the multiplexer 10 maintains the current bus request signal generation state even if another bus request signal is generated. In this state, the bus requester is connected to a bus busy signal through the DTB arbitration bus of the VME bus.

) Is maintained until low.

신호가 액티브상태(low)에서 디액티브되는 순간(high), 카운터(30)는 업카운팅하여 "01"이 된다. 상기 카운터(30)의 "01"출력에 의해 디코더(40)는 제2선택신호를 출력하며, 이로 인해 제2버스중재부(60)가 인에이블된다. 이후 제2버스중재부(60)는 상기 멀티플렉서(10)의 버스요구신호에 따른 버스중재를 하는데, 우선권은 BR₂ ^*→ BR₁ ^*→BR₀ ^*→ BR₃ ^*의 순서이다. 이때 이중 어느 하나라도 액티브 상태(low)가 되면, 제어신호발생부(20)는 "로우" 상태의 제1제어신호를 발생하여 멀티플렉서(10)에서 현상태의 버스요구신호를 유지할 수 있도록 하며, 제2버스중재부(60)는 상기의 우선권에 따라 해당 버스요구신호의 승인신호를 발생한다.When the bus is arbitrated as described above, data is transferred to the VME bus by the master of the VME bus. At this time

When the signal is deactivated in the active state high, the counter 30 is counted up to " 01 ". The decoder 40 outputs the second selection signal by the " 01 " output of the counter 30, thereby enabling the second bus arbitration unit 60. FIG. Thereafter, the second bus arbitration unit 60 performs bus arbitration according to the bus request signal of the multiplexer 10, and the priority is BR ₂ ^* → BR ₁ ^* → BR ₀ ^* → BR ₃ ^* . At this time, if any one of the active state (low), the control signal generator 20 generates a first control signal of the "low" state to enable the multiplexer 10 to maintain the current bus request signal, The two bus arbitration unit 60 generates an acknowledgment signal for the corresponding bus request signal in accordance with the above priority.

신호를 디액티브 시키는 순간, 카운터(30)는 카운트값을 "1"로 증가시킨다.Subsequent operations are the same as described above, where the bus master

Upon deactivating the signal, the counter 30 increments the count value to "1".

Accordingly, the output of the counter 30 becomes "10", and the decoder 40 generates the third selection signal by the counter value, thereby enabling the third arbitration unit 70. The subsequent operation is the same as the above-described process.

In sum, the priorities of the operations of the first to fourth bus arbitration units 50 to 80 are periodically changed according to the BBSY signal. That is, as the output of the counter 30 changes from "00 → 01 → 10 → 11 → 00…”, the decoder 40 causes the first bus arbitration unit 50 to the second bus arbitration unit 60 to 3 Bus Arbitration Unit (70) → 4th Bus Arbitration Unit (80) By enabling in order, BR ₃ ^* , BR ₂ ^* , BR ₁ ^* , BR ₀ ^* → BR ₂ ^* → BR ₁ ^* , BR ₀ ^* , BR ₃ ^* → BR ₁ ^* , BR ₀ ^* , BR ₃ ^* , BR ₂ ^* → BR ₀ ^* , BR ₃ ^* , BR ₂ ^* , BR ₁ ^* →. Will change in the order of. At this time, the arbitration time of arbitrating the bus by the priority according to the output value of the counter 30 is equal to the propagation time of the counter 30 and the bus arbitration unit.

Referring to FIG. 3, the bus arbitration process for the bus request signal generated when the value of the counter 30 is "00" will be described in detail.

In FIG. 3, the MUX M1-M4 is the multiplexer 30 in FIG. 3, the inverters IG1-IG4, the OA gate OG1, and the AND gate NG1 are the control signal generator 20, and the NAND. The gates NG2-NG5 are the first bus arbitration section 50. In addition, the NOA gate NO1 generates a "high" signal only when the output of the counter 30 is "00" as part of the decoder 40 to enable the first bus arbitration unit 50.

Therefore, when the output of the counter 30 is not "00", the output of the NOA gate NO1 becomes "low". Therefore, the first arbitration unit 50 is irrelevant regardless of the occurrence of the bus request signal BR ₃ ^* -BR ₀ ^* . NAND gates N2-N5 do not generate a bus approval signal by generating a "high" signal. That is, the first bus arbitration unit 50 does not perform bus arbitration. However, when the output of the counter 30 is "00", the output of the NOA gate NO1 becomes "high", so that the counter 30 operates as the first selection signal. Thus, the bus request signal BR ₃ ^* -BR ₀ ^* A high signal is applied to each of the AND gates N2-N5 to be input to make the enable state. Accordingly, when the arbitrary bus request signal BR ₃ ^* -BR ₀ ^* becomes active, the first bus arbitration unit 50 generates a bus approval signal in a low state to the corresponding AND gate. That is, in the configuration of the fourth arbitration unit 80, the output of the NAND gate NG2 is the input of the NAND gate NG3-NG5, and the output of the NAND gate NG3 is the input of the NAND gate NG4-NG5. The output of the NAND gate NG4 is again applied to the input of the NAND gate NG5, so that the priority of the bus arbitration of the first bus arbitration section 50 is BR ₃ ^* → BR ₂ ^* → BR ₁ ^* → BR _In order of ₀ ^* .

First, when any bus request signal of BR ₃ ^* -BR ₀ ^* is activated in a "low" state, it is applied to the inverters IG1-IG4 through the MUX M1-M4, and the inverters IG1-IG4 are connected to these. The signal is inverted and applied to the NAND gates NG2-NG5, respectively, and simultaneously applied to the oragate OG1.

신호의 상태는 버스가 사용되고 있는 상태가 아니므로 "하이"상태이며, 이로 인해 낸드게이트(NG1)는 "로우" 신호로 출력하게 된다. 따라서 MUX(M1-M4)는 (A) 단자측 입력을 선택하게 되어 이후 발생되는 버스요구신호의 영향을 받지 않도록 현상태를 유지시킨다. 이때 낸드게이트(NG2-NG5)는 발생한 버스요구 신호에 대하여 버스 승인 신호를 발생하며, 이 상태는

신호가 액티브상태(low)로 천이될 때까지 계속된다. 이때 상기 낸드게이트(NG2-NG5)를 통한 버스승인신호

의 논리상태는 하기와 같다.OA gate OG1 thus generates a " high " signal by the active bus request signal. At this time

The state of the signal is a "high" state because the bus is not in use, and thus the NAND gate NG1 outputs a "low" signal. Therefore, the MUX (M1-M4) selects the (A) terminal side input and maintains the present state so as not to be influenced by a subsequent bus request signal. At this time, the NAND gate NG2-NG5 generates a bus acknowledgment signal with respect to the generated bus request signal.

It continues until the signal transitions to the active state (low). At this time, the bus approval signal through the NAND gates NG2-NG5.

The logic state of is as follows.

신호가 액티브 상태(low)가 되면 낸드게이트(NG1)의 출력이 "하이"상태, 즉 제2제어신호가 되므로 MUX(M1-M4)는 다시 B단자의 입력을 선택하게 된다.Since the above

When the signal becomes active (low), the output of the NAND gate NG1 becomes the "high" state, that is, the second control signal, so the MUX M1-M4 selects the input of the B terminal again.

신호가 디액티브상태(하이)로 천이되며, 이로 인해 카운터(30)로는 클럭을 공급하게 된다. 따라서 제1버스중재부(50)의 버스중재는 종료되고, 제2버스중재부(60)가 인에이블된다.After completing the data transfer through the VME bus,

The signal transitions to the inactive state (high), which causes the counter 30 to supply a clock. Accordingly, the bus arbitration of the first bus arbitration unit 50 is terminated and the second bus arbitration unit 60 is enabled.

An operation of FIG. 3 will be described with reference to the timing diagram of FIG. 4.

신호가 액티브되며, 이로 인해 (4c)와 같이

신호가 "로우"인 구간에서 BR₂ ^*를 발생한 버스요구신호부가 VME 버스를 통해 데이터를 전송한다. 이후 상기 (4c)의

신호가 디액티브되는 순간 카운터(30)는 "01"를 출력하게 된다. 따라서 제2버스중재부(60)가 인에이블되며, 상기 (4b)와 같이 BR₁ ^*신호는 제2버스중재부(60)에서 (4e)와 같은 버스승인신호

을 발생한다.Referring to the process of FIG. 4A, first, when BR ₂ ^* and BR ₁ ^* are generated at the same time as in (4a) and (4b), the NAND gate NG3 is set by the bus arbitration priority of the first arbitration unit 50. First through

The signal is active, which causes (4c)

In the section where the signal is "low", the bus request signal unit generating BR ₂ ^* transmits data through the VME bus. After (4c)

The moment the signal is deactivated, the counter 30 outputs "01". Therefore, the second bus arbitration unit 60 is enabled, and the BR ₁ ^* signal is the bus approval signal such as 4e in the second bus arbitration unit 60 as shown in (4b).

Occurs.

In this case, t1 is a bus arbitration time which is a transmission time of the first bus arbitration unit 50 and the counter 30, and t2 is a transmission time of the first bus arbitration unit 50.

신호가 BR₁ ^*신호보다 조금 늦게 발생된 경우(ta＞tb) (4m)과 같은 낸드게이트(NG1)의 "로우"상태의 제1제어신호에 의해 MUX(M2, M3)는 (4h)와 같이

신호를 "하이" 상태로, (4i)와 같이

신호를 "로우"로 하여 최초 버스요구신호 발생상황을 유지시킨다. 따라서 낸드게이트(N4)과 (4e)과 같이 먼저

신호를 발생하며, BR₁ ^*신호를 발생한 버스요구부가 먼저 VME 버스를 통해 데이터를 전송하며 (4i)와 같이

신호가 "로우"상태로 만든다.Secondly, the process of FIG. 4b is explained.

When the signal is generated a little later than the BR ₁ ^* signal (ta> tb), the MUX (M2, M3) is equal to (4h) by the first control signal in the "low" state of the NAND gate NG1 equal to (4m). together

Leave the signal "high", as in (4i)

The signal is " low " to maintain the initial bus request signal generation status. Therefore, like NAND gates (N4) and (4e),

Signal is generated, and the bus request unit generating the BR ₁ ^* signal first transmits data through the VME bus, as shown in (4i).

Make the signal "low".

신호가 "하이"상태로 디액티브되는 순간 낸드게이트(NG1)가 (4m)와 같이 "하이"상태의 제2제어신호를 발생하므로 MUX(M1-M4)는 다시 A단자측 입력을 선택하며, 이때 MUX(M2)는 (4h)와 같이 "로우"상태의

신호를 선택한다. 이때 상기 제2제어신호에 의해 카운터(30)는 "01"을 출력하며, 따라서 디코더(40)는 제2선택신호를 출력하고, 이로 인해 제2버스중재부(60)가 인에이블된다.Since the above

As the NAND gate NG1 generates the second control signal in the "high" state as (4m) as soon as the signal is deactivated to the "high" state, the MUX (M1-M4) selects the A terminal side input again. At this time, MUX (M2) is in the "low" state such as (4h).

Select the signal. At this time, the counter 30 outputs "01" by the second control signal, and thus the decoder 40 outputs a second selection signal, thereby enabling the second bus arbitration unit 60.

신호는 제2버스중재부(60)에서 중재한다.Thus above

The signal is mediated by the second bus arbitration unit 60.

에 의해 수행되며, 카운터(30)의 클럭은

신호가 액티브 상태(low)에서 디액티브상태(high) 상태로 천이되는 순간 공급된다.In summary, the initialization of the counter 30 is a system reset signal.

Is performed by the clock of the counter 30

The signal is supplied at the moment when the signal transitions from the active state to the high state.

In addition, the logic of the control signal generator 20 for generating a control signal for selecting the input terminal of the multiplexer 10 is as follows.

의 논리식은 하기와 같다.Also bus approval signal

The logical expression of is as follows.

의 논리식과 같이 구성하면 된다.Accordingly, the first to fourth bus arbitration units 50-80 may be configured according to the output state of the counter 30.

It can be configured as the logical expression of.

As described above, in a system using a VME bus, multiple bus masters may generate a bus request signal with the same priority, thereby minimizing bus arbitration time and maintaining a corresponding state when a bus request signal is generated through a multiplexer. This has the advantage of eliminating anti-mediation errors.

Claims (1)

A bus arbitration circuit of a system using a VME bus, comprising: a multiplexer for inputting a bus request signal of each bus master when a second control signal is generated and maintaining a current bus request state when a first control signal is generated; and a bus request signal from the multiplexer. A counter that generates the first control signal when generated and generates a second control signal when a bus use signal is generated, and a counter that operates every time the bus use signal is released to generate count data for giving the same priority to bus arbitration; And a decoder for generating a selection signal according to the output of the counter, and an output of the multiplexer. Round robin bus arbitration circuit, characterized in that the configuration.

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