JP2669109B2 - Bus access arbitration circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system for a computer system, and more particularly to a bus access arbitration circuit when a plurality of bus masters share one bus for access.

(Prior Art) FIG. 3 is a block diagram showing an example of a conventional bus access arbitration circuit described in JP-A-63-186354.

This circuit uses the bus use request signal REQ1 that is generated asynchronously.
To REQn, a first flip-flop, a priority encoder to encode the synchronized signals I1 to In, a second flip-flop to latch the encoded signals A0 to Am, and a latched encoded output signal It is provided with a decoder which produces bus use permission signals ACK1 to ACKn from Q0 to Qm, and a circuit which produces a strobe signal for the decoder.

This circuit has a fixed priority for each bus use request, and conflicts when a plurality of bus use requests are synchronized at the same timing in the first flip-flop, that is, when a conflict occurs. An operation of selecting one having the highest priority from the bus use requests and outputting the bus use permission is performed.

The priority is determined by the I1 to In inputs of the priority encoder.

In the example of FIG. 3, if I1 has the highest priority and In has the lowest priority, the bus use request has the highest priority REQ1 and the lowest REQn.

(Problems to be Solved by the Invention) In the above-mentioned conventional technique, the priority order is fixedly set, and since no consideration is given to sinking,
There has been a problem that a bus use permission is not issued forever for a low priority bus use request.

 Subduction refers to the following phenomena.

As a result of arbitration by the fixed priority method when the bus use requests conflict, the bus use permission is first output for the bus use request having the highest priority, and the subsequent arbitrations sequentially have higher priority. The bus use permission is output in order. At this time, if a new high-priority bus use request is generated before the low-priority bus use request is output, the low-priority bus use request is issued with the bus use permission. Instead, a bus use permission is issued for a high-priority bus use request. Therefore, while the high priority bus use request is repeatedly generated, the bus use permission for the low priority bus use request is not output forever. This phenomenon is called sinking.

The problem to be solved by the present invention is to provide a bus access arbitration circuit that prevents the sinking of the fixed priority system in the bus access arbitration circuit described above and gives each bus master an average bus use opportunity. It is in.

(Means for Solving the Problems) In order to solve the above problems, when a plurality of bus masters share one bus for access, the first stage of a plurality of arbitration circuits connected in series, the number of which is the same as the number of bus masters. A request from the bus master is input to the bus access arbitration circuit that arbitrates conflicting accesses and issues a bus use permission.
Each of the arbitration circuits inputs a result of the contention arbitration and a bus use request, and operates by a logic gate for detecting a bus use request that has been waited without a bus use permission and an enable signal to operate the bus use request. A priority circuit for outputting a request having a higher priority from among the requests, outputting a disable signal when there is an active output, and outputting an enable signal when there is no active output, further comprising the arbitration circuit of each stage A logic gate output to the arbitration circuit of the next stage as a bus use request, and a disable signal is output to the preceding priority circuit when the output of the priority circuit has an active output. And a path for outputting an enable signal when there is no input signal, and the output of the priority circuit of each stage of the arbitration circuit is input to one bus access circuit. A bus use permission logic gate for determining a request and outputting an arbitration result as an input of the logic gate, and arbitrating conflicting accesses by always enabling the priority circuit at the last stage; It is characterized by issuing a bus use permit.

(Operation) The bus access arbitration circuit configured as described above operates as follows. The contention arbitration result and the bus usage request are input to the logic gate, and the bus usage request is detected when the arbitration result does not permit the bus usage and the bus usage request is input at that time. When a plurality of arbitration circuits are connected in series to form a bus access arbitration circuit, the logic gate output of the preceding stage is used as a bus use request for the second and subsequent stages. The bus use request is also input to the priority circuit and operated by the enable signal, whereby the one with the higher priority is selected and output. This enable signal is input from the next-stage priority circuit when all outputs of the next-stage priority circuit are inactive. The bus use permission decision logic gate inputs the priority circuit outputs of the respective stages, and outputs them when they do not match, thereby determining one bus access request. That is, since the active circuit does not output an active signal after the next stage of the priority circuit that outputs the active signal and is not enabled before the previous stage, only one of the active priority circuits outputs the signal. Output from the bus use permission decision logic gate. The bus use permission by the bus use permission determination logic gate output is input to the logic gate of the arbitration circuit for the next arbitration operation.

Embodiments Embodiments of the bus access arbitration circuit according to the present invention and the arbitration circuit used in the present invention will be described below.

FIG. 1 is a block diagram of one embodiment, and FIG. 2 is a timing chart for explaining the operation. In FIG. 1, A1 and A2 to An are arbitration circuits and FF1 is a flip-flop, which inputs n bus use request signals RQ1 to RQn, latches them, and outputs bus use request signals LRQ1 to LRQn. PR1 is flip-flop F
This is a priority circuit that receives the output of F1 and selects a bus use request signal with high priority, and has an output terminal GS and an input terminal EI for cascade connection. It operates when an enable signal is input to the EI pin. When all outputs are inactive, enable signal is output from GS pin, and if there is active output, disable signal is output. G11 to G1n are logic gates for detecting a bus use request that is awaited without issuing a bus use permission, using the output of the flip-flop FF1 and the arbitration result as inputs. These flip-flop FF1, priority circuit PR1 and logic gates G11 to 1n
Constitute the arbitration circuit A1, and the insides of the arbitration circuits A2 to An are the same as the bus access circuit A1.

When cascading multiple arbitration circuits A1 to An,
The GS output is connected to the EI input of the arbitration circuit Ax in the previous stage,
It is connected to the arbitration circuit A (x-1) at the lower stage as an enable signal for the arbitration operation. The EI input of the final stage arbitration circuit An is connected to the ground, and the first stage GS output is not connected to anything.

Outputs RQ21 to RQ2n of logic gates G11 to G1n of the arbitration circuit A1
Is input as a bus use request signal to a flip-flop (FF2) not shown as an input of the second arbitration circuit A2.
Outputs of logic gates (G21 to G2n) (not shown) of the arbitration circuit A2 are input to a flip-flop (FF3) (not shown) of the arbitration circuit (A3) (not shown). As described above, the gate logic output signals RQx1 to RQxn are input to the arbitration circuit one stage higher as a bus use request signal.

AKOR1, AKOR2 to AKORn are bus use permission decision logic gates, and the priority circuits PR1 to PR of the above arbitration circuits A1 and A2 to An.
n output AK11 to AK1n, AK21 to AK2n, ... AKn1 to AKnn are input to determine one bus access request, and the arbitration result is output. The outputs AKx1 and AKx2 to AKxn of the priority circuits PR1 to PRn are input to the bus use permission decision logic gate AKORx. Bus use enable decision logic gates AKOR1, AKOR2 to AKORn and AKx1 to AK
The connection relationship of the xn signal is as follows. Ie
The AKOR1 circuit receives AK11 to AKn1 signals, the AKOR2 circuit receives AK12 to AKn2 signals, and the AKORn circuit receives AK1n to AKn.
n signal is input. Therefore, the bus use permission decision logic gates AKOR1 to AKORn circuits are n-input circuits. The FFA is a flip-flop that latches the outputs of the bus use permission decision logic gates AKOR1 to AKORn and outputs a bus use permission signal. The outputs of the bus use permission decision logic gates AKOR1 to AKORn are input to the logic gates G11 to 1n (... Gn1 to Gnn) of the arbitration circuits A1 to An via the flip-flop FFA. CK is a latch signal generation circuit.

The operation of the present invention will be described below with reference to the drawings. For ease of explanation, the number of bus use requests is three, that is, n = 3 in FIG. RQ1 has the highest priority and RQ3 has the lowest priority. In FIG. 2, RQ21 to RQ23, RQ31 to RQ3
The signals of 3, AK11 to AK13, AK21 to AK23 and AK31 to AK33 are drawn in the form of a bus. The shaded areas are indefinite or meaningless. The numbers in parentheses indicate the level of each signal. “1” is “high”, “0” is “low”, and the left is the youngest signal.

First, the bus use requests RQ1 to RQ3 become "low" and issue requests almost simultaneously (FIG. 2). When this is latched by the flip-flop FF1 of the arbitration circuit A1 at the rising edge of the latch signal RCK, the priority circuit PR1 outputs the signal RQ having the highest priority among the signals whose inputs are active.
Select 1 to make signal AK11 "low" (Fig. 2).
At the rise of the latch signal RCK, the input signal R of the arbitration circuit A2
Since the input signals RQ31 to 33 of Q21 to RQ23 and the arbitration circuit A3 are all "high", the output signals AK21 to AK23 and AK31 to AK33 of the arbitration circuits A2 and A3 are all "high". Therefore,
Among the outputs of the bus use permission decision logic gates AKOR1 to AKOR3, only the output of AKOR1 becomes "low". The input of the flip-flop FFA is latched by the rising edge of the latch signal ACK output with a certain delay time from the latch signal RCK, and the ACK1 signal becomes "low", so the bus use request signal RQ1 is not permitted to be used. It has been released (Fig. 2).

The bus use permission signals ACK1 to ACK3 are fed back to the arbitration circuits A1 to A3 to detect a bus use request that is in the process of requesting to use the bus and the bus use request has not been issued. In the above description, the bus use request signal is not output to the bus use request RQ2 signal and the RQ3 signal, so that the RQ22 signal and the RQ23 signal become "low" (FIG. 2).

When the bus master permitted to use the bus uses the bus, the bus busy signal BUSY becomes “low”, and when the bus master finishes using the bus, the BUSY signal becomes “high”.

Latch signal creation circuit RCK when BUSY signal becomes "high"
Outputs a latch signal RCK. The arbitration circuit A1 latches RQ1 “high”, RQ2 “low”, RQ3 “low” by the rising edge of the RCK signal, and the arbitration circuit A2 latches RQ21 “high”, RQ22 “low”, RQ23 “low” (No. (Fig. 2). Then, the arbitration circuits A1 and A2 perform arbitration based on the priority order and output the AK22 signal "low" (FIG. 2). At the same time, the GS terminal of the arbitration circuit A2 outputs a signal E2 to indicate that an active output is present among the AK21 to AK23 signals.
"Low" is output to 1 and is input to EI of the arbitration circuit A1 (Fig. 2). The arbitration circuit A1 sets all the AK11 to AK13 signals to "high" when the E21 signal becomes "low" (Fig. 2). Therefore, at this time, only the output of AKOR2 is "low" among the bus use permission decision logic gates AKOR1 to AKORn.

After a certain delay time from the output of the latch signal RCK, the latch signal ACK is output from the latch signal generation circuit CK, the bus use permission signal ACK2 becomes “low”, and the bus use permission is issued in response to the bus use request RQ2 ( (Fig. 2).

The bus use permission signals ACK1 to ACK3 are fed back to the arbitration circuits A1 to A3, and the waiting bus use request is detected, and the RQ23 signal becomes "low" and the RQ23 signal becomes "low" (FIG. 2).

When the bus master that has received the bus use permission finishes using the bus and the bus busy signal BUSY becomes “high”, the latch signal generation circuit CK outputs the latch signal RCK.

Latch signal RCK signal causes arbitration circuit A1 to go to R
Latch the Q1 signal “high”, the RQ2 signal “low”, and the RQ3 signal “low”. At this point, the arbitration circuit A1 detects that the RQ2 signal has again output the bus use request (FIG. 2). In addition, the arbitration circuit A2 latches the RQ21 to RQ23 signals,
A3 latches the RQ31 signal “high”, the RQ32 signal “high”, and the RQ33 signal “low” and outputs the AK33 signal “low” (second
Figure), AK21 to A of arbitration circuit A2 by setting E32 signal to "low"
Set all K23 signals to "high" (Fig. 2). Arbitration circuit A
2 outputs the E21 signal "low" when the E32 signal is "low" and sets all the outputs AK11 to AK13 of the arbitration circuit A1 to "high".

At this time, bus use permission decision logic gates AKOR1 to AKO
Since only the output of AKOR3 is low in R3, the bus use permission signal ACK3
Is output as "low" (Fig. 2).

The output ACK1 to ACK3 of the flip-flop FFA is fed back, and as a result of detecting the waiting bus use request while issuing the bus use request, the RQ22 signal output from the arbitration circuit A1 becomes "low". (Fig. 2).

When the bus master permitted to use the bus finishes using the bus and the bus busy signal BUSY changes from “low” to “high”, the latch signal RCK is output and the arbitration circuit A1 outputs the RQ1 signal “low” and the RQ2 signal “low”. , Latch the RQ3 signal "high",
The arbitration circuit A2 has RQ21 signal “high”, RQ22 signal “low”, RQ
23, the signal "high" is latched, and the arbitration circuit A3 latches the signals RQ31-RQ33 "high" (FIG. 2). Here, since the outputs AK31 to AK33 of the arbitration circuit A3 are all "high", the E32 signal is also "high".

The arbitration circuit A2 outputs the AKK22 signal "low" and the E21 signal "low" (Fig. 2), and the outputs AK11 to AK13 signals of the arbitration circuit A1 become "high". Therefore, the bus use permission decision logic gate AKOR2 Only the output will be "low". When the latch signal ACK rises, the ACK2 signal goes low,
A bus use permission is issued for the bus use request RQ2 (FIG. 2).

The above operation (from FIG. 2) indicates the following. That is, the fixed priority of the bus use request is RQ.
Although the 1 signal is higher, the RQ2 signal was "low" first, so the bus use permission was issued before the RQ1 signal, and the first-come-first-served arbitration was performed.

The bus use permission signals ACK1 to ACK3 are fed back, and the arbitration circuit A1 outputs the RQ21 signal “low”, the RQ22 signal “high”, and the RQ23 signal “high”.

In the next arbitration, only the RQ1 signal is "low", so that the ACK1 signal is "low".

As described above, the arbitration circuit A1 first arbitrates the bus use request, the arbitration circuit A2 arbitrates the one-time waiting bus use request, and the arbitration circuit A3 arbitrates the two-waiting bus use request. To do. Since the arbitration circuits A1 to A3 have the highest priority in A3 and the lowest in A1, the higher the number of waiting times for bus use requests, the higher the priority.

Therefore, the arbitration operation uses a priority method for a plurality of bus use requests generated at the same time, but detects a request for a bus use request generated when there is a waiting bus use request. The bus permission is issued in the order of the so-called first-come-first-served arbitration.

(Effects of the Invention) As described above in detail, according to the present invention, the priority system and the first-come-first-served system can be combined by providing a means for detecting a waiting bus use request and giving priority to the use. A bus access arbitration circuit of a different form can be realized, and the sinking seen in the conventional fixed priority system can be completely prevented.

[Brief description of the drawings]

1 and 2 are diagrams for explaining a bus access arbitration circuit according to the present invention. FIG. 1 is a block diagram, FIG. 2 is an operation timing diagram, and FIG. 3 is a conventional bus access arbitration circuit. It is a block diagram. A1 to An ... Arbitration circuit, AKOR1 to AKORn ... Bus use permission decision logic gate, CK ... Latch signal creation circuit, FF1 ... Flip-flop, FFA ... Flip-flop, G11-G1n
...... Logic gate, PR1 …… Priority circuit, ACK1 to ACKn…
... bus use enable signal, AK11 to AK1n ... bus use enable signal from arbitration circuit A1, AK21 to AK2n ... bus use enable signal from arbitration circuit A2, AKn1 to AKnn ... bus use enable signal from arbitration circuit A3 , ACK: latch signal, BUSY: bus busy signal, E21: enable signal for arbitration circuit A11,
E32: Enable signal for arbitration circuit A2, En (n-
1) Enable signal for arbitration circuit A3, LRQ1 to LR
Qn ... Latched bus use request signal, RQ1 to RQn ... Bus use request signal, RQ21 to RQ2n ... Bus wait request signal that has been waited once. RQ31 to RQ3n: Bus use request signals waited twice, RQn1 to RQnn: Bus use request signals waited n-1 times, RCK: Latch signal.

Claims (1)

(57) [Claims] 1. When a plurality of bus masters share one bus to access, a request from the bus master is input to the first stage of a plurality of serially connected arbitration circuits, which is the same number as the number of bus masters, and competing access is performed. In the bus access arbitration circuit for arbitrating the bus use request, each of the arbitration circuits receives the result of the contention arbitration and the bus use request as inputs, and receives the bus use request that has been waiting without the bus use permission being issued. Operates by a logic gate to be detected and an enable signal, outputs a bus request having a higher priority among the bus use requests, outputs a disable signal when there is an active output, and outputs an enable signal when there is no active output. And a logic gate output of the arbitration circuit of each stage is input to the arbitration circuit of the next stage as a bus use request. A path, outputting an disable signal to the preceding priority circuit when there is an active output at the output of the priority circuit;
And a path for outputting an enable signal when there is no active output, inputting the output of the priority circuit of each stage of the arbitration circuit to determine one bus access request, A bus access arbitration, comprising a bus use permission determination logic gate for outputting an arbitration result, and arbitrating a conflicting access and issuing a bus use permission by always enabling the priority circuit at the last stage. circuit.