JPS621059A - Shared memory access method for multi-microprocessor system - Google Patents

Abstract

PURPOSE:To minimize the deterioration of throughput in case an access has the conflict by providing the random access memories of the same address constitution to the microprocessors respectively. CONSTITUTION:In a data reading mode each microprocessor gives an access individually to a random access memory corresponded respectively and reads out data independently of other microprocessors. When a data writing request is given from a certain microprocessor, the same data are written simultaneously to the same address position of all random access memories respectively. If the writing requests have conflicts, the writing processes are carried out according to the prescribed priority. Thus the physical plural memories function as a single logic shared memory consisting of the same data.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a multiprocessor system consisting of a plurality of microprocessors.
This paper concerns shared memory access methods in microprocessor systems.

2. Description of the Related Art Conventionally, various methods such as those described below are known as methods for accessing a shared memory from a plurality of microprocessors.

(1) Microprocessor (CPU) standby (WA)
A method of using IT) signals to make one microprocessor standby when there is contention for access to the shared memory (2) A method of shifting the phase of each microprocessor to avoid outputting access signals at the same time (3) A method that uses a microprocessor with a symmetrical fetch cycle and an execution cycle to avoid conflicts in memory access. (4) A method that arbitrates access requests from each processor by providing a dedicated circuit. (5) Has a HOLD signal. It consists of a general-purpose processor and a one-chip microcontroller. Normally, the one-chip microcontroller operates on the memory within its chip, and a hold request is made only when the one-chip microcontroller accesses the shared memory. (6) One microprocessor uses the memory During the access, the access of the other microprocessor is prohibited by software.Problems to be Solved by the InventionAs mentioned above, various memory access methods have been developed in the past. It is configured on the premise that the shared memory is physically composed of only one memory, and that there is only one line to control it. Therefore, when accesses from each microprocessor overlap, simultaneous access to the shared memory is impossible, and processors other than the microprocessor that granted access must wait, resulting in a problem in which throughput decreases due to access contention. was there. Currently, there is memory called 2-bottom RAM, but its memory capacity is small and it is not expandable, and it is not known that it has three or more ports.

The present invention was made to solve the above problems, and
The object of the present invention is to provide a shared memory access method that can minimize reduction in throughput when accesses from multiple microprocessors compete.

Means for Solving the Problems In order to solve the above problems, the present invention provides a random access memory with the same address configuration for each microprocessor in a multiprocessor/system consisting of a plurality of microprocessors. To read data from the access memory, each microprocessor individually accesses the corresponding random access memory, and to write data from each microprocessor, write requests are made according to predetermined priorities of the microprocessors. The write address of the microprocessor that received the write request is simultaneously selected in all the random access memories, and the write data output from the microprocessor that made the write request is written to all the memories at the same time.

Operation When each microprocessor reads data, each microprocessor individually accesses its corresponding random access memory and reads the data independently of the other microprocessors.

On the other hand, when a data write request is received from any microprocessor, the write address output by the microprocessor making the write request is sent to all random access memories, and the same address is selected simultaneously in all memories. Then, the same data is simultaneously written to the same address location in all random access memories. When write requests from multiple microprocessors compete, write processing is executed according to predetermined priorities. Therefore, according to the present invention, although it physically has a plurality of memories, it functions logically as one shared memory consisting of the same data. Therefore, in the present invention, there is no reduction in throughput even if read requests compete, and a wait state only occurs in write operations when write requests compete, so the system as a whole The reduction in throughput can be minimized.

Example The present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a shared memory in a multi-microprocessor system using four microprocessors constructed by applying the method of the present invention.
is a microprocessor (CPU); 28 to 2d are random access memories (hereinafter abbreviated as "memory") having the same address configuration provided corresponding to each of the microprocessors 1a to 1d; 3a to 3d are microprocessors 1a to 1d; 3-state address latch circuit that latches the write address from 1d, 4a to 4d are each memory 2
Address selector t for selecting designated addresses a to 2d
5a to 5d are three-state data latch circuits that latch write data output from each of the microprocessors 1a to 1d, and 5a to 6d are bidirectional bus drivers that send and receive write and read data to and from each memory 28 to 2d. be.

In the above circuit, the method of the present invention is implemented as follows. That is, in the case of a data read operation from the memory, for example, when a read request is received from the microprocessor 1a, the read address output from the microprocessor 1a is given to the address selector 4a.

The address selector 4a selects the address location in the memory 2a, and transfers the data at the address location to the bus driver 6.
a to the microprocessor 1a. Similarly, the other microprocessors 1b, 1c, and 1d independently read out target data from the corresponding memories 2b, 2c, and 2d, respectively. In this way, in the case of a data read operation, each microprocessor can perform the read operation completely independently of the other microprocessors.

On the other hand, the data write operation is executed as follows. That is, for example, when a write request is received from the microprocessor 1a, the write address and write data output from the microprocessor 1a are sent to the address strobe signal (ASa) and the data strobe signal (
DSa).

-H is latched by the write signal (WRa) into the 3-state address latch circuit 3a and 3-state data latch circuit 5a, respectively. At the same time, a write request signal (WREQa) from the microprocessor 1a is sent to a write/read control circuit (described later), and the write/read control circuit checks whether there is no conflict between write requests from other microprocessors or whether there is a conflict between write requests. In some cases, according to the priority determined by the processing priority circuit described later,
A write acknowledge signal (WACKa) is sent to the 3-state terminals of the 3-state address latch circuit 3a and 3-state data latch circuit 5a, and the data is latched into the latch circuits 3a and 5a using the output gates of each latch circuit. Sends the write address and write data towards the memory side. At this time, the other 3-state address latch circuit 3b.

3c, 3d and 3-state data latch circuits 5b, 5
Since no write acknowledge signal is applied to the three-state terminals c and 5d, the output gates are closed and in a high impedance state. Therefore, the write address output from the 3-state address latch circuit 3a to which the write acknowledge signal (WACKa) is applied is given to all address selectors 4a to 4c, and is also output from the 3-state data latch circuit 5a. Write data is written to all bus drivers 6a.
~6d.

As a result, each memory 2a to 2d is connected to each address selector 4.
The same address position is selected by bus drivers a to 4d and each bus driver 6a to 6d, and the same data is written to the same address position.

The microprocessor that has written can continue main processing immediately after outputting the data, but the writing of the next data from the same microprocessor is on standby (WIT) until writing to all memories is completed.

As described above, when there is a data write request, the write data from the microprocessor that requested the write is written to the same address location in all memories at the same time. Therefore, although the memories 2a to 2d are physically plural, they logically function as one shared memory consisting of the same data.

FIG. 2 shows an example of a processing priority circuit when write requests conflict. When write requests from each of the microprocessors 1a to 1d conflict, the circuit gives a predetermined priority to each microprocessor. given,
The write operation to the memory is executed according to the priority order.

That is, in FIG. 2, 2ta to 21d are write request flip-flops corresponding to each microprocessor;
2 is a priority encoder% 23 is a decoder,
24a to 24d are gate circuits that receive write request signals (W) from each microprocessor 1a to ld (FIG. 1).
When REQa) to (WREQd) are given, the corresponding write request flip-flops 21a to 21d memorize that there is a write request from each microprocessor. For this write request, the priority encoder 22 and decoder 23 determine the processing priority in the event of a conflict, and the decoder 23 returns a write acknowledge signal (WACKa) to the microprocessor with a higher priority, for example, the Eva microprocessor 1a. Ru. As a result, the 3-state address latch circuit 3 in FIG.
As described above, the write address and write data are sent from the data latch circuit 5a and the data latch circuit 5a to all the memories 2a to 2d, and the same data is written to all the memories at the same time. In this way, the decoder 23 outputs the write acknowledge signal (WACKa) according to the priority order.
.about.(WACKd) are sent sequentially, and each microprocessor executes write operations sequentially in accordance with priority. Furthermore, when there is a write request from any of the microprocessors, the priority encoder 22 generates a write request presence signal and supplies it to a write/read control circuit to be described later.

FIG. 3 shows a configuration example of a write/read control circuit for controlling write operations and read operations to the memory. For simplicity, only the circuit portion corresponding to the microprocessor 1a is shown. In the figure, 31a is a write start flip-flop, 32a is a shift register (8
bit), 33a to 35a are write control flips 70
The knob, 36a, is a readout start flip-flop, 37a.
~40a is an acknowledge reply flip-flop, 41a
is write control flinoa "70tsu7', 42a~42d
is a write completion flip-flop 70, and 43.44 is a write completion reset flip-flop.

When writing is requested, write start flip 70 knob 31
In response to the write request signal (WREQa), the shift register 32a, write control flip 70 knobs 33a, 34a, 35a, etc. receive the clock signal (CLKa), provided that the corresponding microprocessor 1a is not in read access. Accordingly, the address strobe signal (ASa) and cheetah strobe signal (D
Sa), outputs a write signal (WRa), and executes data writing as explained in FIG.

At the time of a read request, the read start flip-flop 36
It is used on the condition that the read signal (RDa) is given to a, and the write start flip-flop 31a is not set, that is, the writing is not in progress, or if the write process is completed, the write process is completed. An acknowledge signal is returned from the acknowledge return flip-flop 38a in consideration of the memory access/cycle time, and reading of data from the corresponding memory 2a is executed as explained in FIG.

Note that the output from each microprocessor is 3 in Figure 1.
Since -H is latched in the stay 1 address latch circuits 3a to 3d and the 3 stay 1 data latch circuits 5a to 5d, a response can be made immediately without waiting for operation.

However, in response to the next write request from the same microprocessor, the output of the acknowledge signal is awaited until the write control flip-flop 41a completes writing the previous data into the customer memory.

The writing is completed by writing control flip-flops 35a to 35d (corresponding to each microprocessor 1a to 1d).
Only 35a is shown in the figure), write completion signal (WENDa)
) to (WENDd) are output, and each write completion flip-flop 42a to 42d is set, thereby detecting the write completion.

Then, write completion reset flip 70 tab 43.
A reset signal from 44 is sent to the write control flip-flop 41a and all write completion flips 70 and 42a.
~42d is reset and the write operation is completed.

FIG. 4 shows an example of a matching diagnostic circuit for detecting matching/mismatching of the data contents of each address of the memo IJ2a to 2d. In the figure, 45 is a fixed period interrupt generation circuit, 46 is a coincidence diagnosis control circuit, 47 is an address/data coincidence detection circuit, and 48a to 48d are write/write/write/write/controllers shown in FIG. 3 provided corresponding to the microprocessors 1a to 1d, respectively. This is a read control circuit.

In the illustrated circuit, when the circuit starts up due to a power-on reset, a synchronous side interrupt, meaning a read request for each memory, is sent to each microprocessor 1a to 1d at a constant period from a constant cycle interrupt generation circuit 45, and each microprocessor updates memory addresses sequentially accordingly. This synchronous interrupt causes each microprocessor 1a to
.about.1d execute reading of data at the same address position in each of the memories 2a to 2d, respectively. At this time, all the microprocessors 1a to 1d are synchronized (WAIT is applied until they are synchronized), and the address/data coincidence detection circuit 47 checks that each address and each data match.
This is to check the contents of each memory.

That is, in response to the synchronization-side interrupt from the constant cycle interrupt generation circuit 45, the coincidence diagnosis control circuit 46 outputs a diagnosis start signal. As a result, the addresses and data read from each of the memories 2a to 2d are routed to the corresponding address shift registers 49a to 49d and data shift registers 50a to 50d, and are exclusively ORed according to the clock signal (CLK). Circuits 51 to 54 check whether each pit matches or does not match, and binary counters 55 and 56 count the number of matched bits to check whether all bits match. Until then, each write/read control circuit 48a to 48d is on standby (WAIT).
)multiply. By outputting a match signal from the AND circuit 57), the check of the contents of each memory is completed, the wait (WAIT) is released, and the operation shifts to the match/mismatch check operation for the next address. Furthermore, when a data match occurs, a mismatch signal can be sent to each microprocessor. Subsequent data applications can be designed freely using software depending on the purpose.

Note that the above-described coincidence diagnosis circuit may not be necessary depending on the system. In this case, the circuitry of the system is significantly reduced.

Effects of the Invention The present invention has the configuration and operation as described above. A random access memory with the same address configuration is provided for each microprocessor, and during read operation, each microprocessor reads data individually from its corresponding random access memory. At the same time, when writing data, the data from the microprocessor that requested the write is simultaneously written to the same address location in all random access memories according to a predetermined priority order. Although it has multiple memories, it logically functions as one shared memory consisting of the same data content, and even if read requests from each microprocessor compete, there is no reduction in throughput, and write requests Even at times, the wait occurs only in accordance with the priority order when write requests conflict with each other, which has the excellent effect of minimizing the reduction in throughput of the multi-microprocessor system as a whole.

In addition, the present invention provides various effects such as faster access time to the shared memory, ease of handling it in the same way as a local memory, and improved data recording performance in which multiple word data are grouped together.

[Brief explanation of drawings]

The drawings show an embodiment of a shared memory device of a multi-microprocessor system configured by applying the method of the present invention, FIG. 1 is a circuit configuration diagram of a shared memory portion, and FIG. 2 is a circuit configuration diagram of a processing priority circuit portion. 3 is a circuit configuration diagram of the write/read control circuit portion, and FIG. 4 is a circuit configuration diagram of the coincidence diagnosis circuit portion. 1a to td...Microprocessor (CPU), 2a
~2d...Random access memory (shared memory),
3a to 3d... 3-state address latch circuit, 4
a to 4d...address selector, 5a to 5d...3
State data latch circuit, 6a to 6d... bus driver (bidirectional).

Claims (1)

[Claims] A random access memory with the same address configuration is provided for each microprocessor, and data can be read from each random access memory by accessing the corresponding random access memory individually from each microprocessor, and by individually accessing the corresponding random access memory from each microprocessor. To write data, all random access memories simultaneously select the write address of the microprocessor that made the write request, according to the predetermined priority of the microprocessors, and write data output from the microprocessor that made the write request. A shared memory access method in a multi-microprocessor system characterized by simultaneous writing to all memories.