JPH07113914B2 - Memory controller - Google Patents

Description

The present invention relates to a memory control device.

[Conventional technology]

An example of a conventional memory control device of this type is shown in FIG.
In FIG. 2, 1 is a device A that receives a request from the device A.
Request reception buffer, 2 is a device B request reception buffer that receives a request from the device B, and 3 is a device C
A device C request receiving buffer for receiving a request from the device 4, a device A buffer reading register for receiving the output of the device A request receiving buffer 1, a device B buffer reading register for receiving the output of the device B request receiving buffer 2, and a device 6 C request reception buffer 3
A device C buffer read register that receives the output of the device, a selector 7 that selects the three outputs of the buffer read registers 4, 5, and 6 and outputs them to the request processing unit 10, and an inter-device priority flip-flop (hereinafter F / F). Abbreviated), and the priority can be changed by the output c of the busy check circuit 9 and the output c of the busy check circuit 9. 9 inputs each bit signal d indicating the type of request of the buffer read registers 4, 5 and 6, the output signal from the inter-device priority F / F8 and the busy signal b of the request processing unit 10, and requests every clock. Based on the busy state of the processing unit 10, the type of each request, and the priority between devices, the selection signal a is sent to the selector 7, and the request processing unit 10 is busy to supply one of a plurality of requests on the port. It is a check circuit. Each clock request may be supplied to the request processing unit 10 by the output of the busy check circuit 9, or a request may be waited for depending on the busy state of the request processing unit 10 (described later).

Reference numeral 10 denotes a request processing unit having a buffer of the main storage device 11 therein, which processes a request input from the request receiving port units 1 to 6 through the selector 7. If data is not registered in the buffer, MMU (main memory unit)
The access signal e is generated. A main storage device 11 is connected to the request processing unit 10 and is accessed from the request processing unit 10. A device A reply register 12 receives the output of the request processing unit 10 and outputs reply data to the device A that is the request request source, and a reference numeral 13 also receives the output of the request processing unit 10 and replies to the device B that is the request request source. Similarly, a device B reply register 14 for outputting data is a device C reply register for receiving the output of the request processing unit 10 and outputting reply data to the device C which is the request request source. In this case, device A,
B and C correspond to I / O processors, arithmetic processing units, and the like.

Next, an actual flow of request processing will be briefly described by taking the device A as an example. 1, 2 and 3 are FIFO (First in First out)
It is a structure buffer.

Requests flow like. Requests entered in 10 get the same result as when they are sequentially processed in the order entered.

In this case, the inside of the request processing unit 10 has a pipeline structure, and there are a plurality of requests of each device, and very complicated processing is performed.

The main storage device 11 is composed of a plurality of banks having an interleaved structure. Therefore, if the main memory device 11 is in another bank, continuous processing is possible regardless of the bank cycle time. This is called a high load environment in the present invention.

Now, assume that the main memory device 11 has a bank cycle time of 10T.
An example will be given in which (T is a clock cycle) and the bank is composed of eight banks, bank 0 to bank 7. Bank 0
Access to bank 0 is prohibited for the next 9T when a certain request accesses
7 can be continuously accessed. That is, every clock access is possible in the order of bank 0 → bank 1 → bank 2 → bank 3 → bank 4 → bank 5 → bank 6 → bank 7. This is called a high load environment. The busy state of the request processing section means that all of the banks 1 to 7 are in use.

[Problems to be solved by the invention]

In recent device design, high integration of LSI has advanced, and memory control devices have become complicated by having an internal cache. Naturally, from such a situation, device simulation was performed in advance and a sufficient logic check was performed, but a logic mistake at the time of hardware design, that is, LSI
It is not possible to detect 100% of the errors (hereinafter, abbreviated as logic errors) caused by the logic design mistake. Therefore, if a logic error occurs in the development inspection phase, the memory controller may have multiple I / O processors and arithmetic operations. Since it is connected to the processing equipment, it has a great impact on the development evaluation of other equipment.
Furthermore, in the case where a logic change inside the LSI occurs, the effect becomes serious.

The conventional example shown in FIG. 2 has a drawback in that it is very difficult to temporarily avoid the logic error when the logic error occurs because no consideration is given to them in advance.

[Means for solving problems]

The memory control device of the present invention has a request reception port unit for receiving a request from each input device, and selects one of the requests according to the busy state of the request processing unit that processes the request and the determination result of the priority between the input devices. 1
Selecting means for selecting and outputting one of them, and "1" when the processing of the preceding request is started by the selection output of the request.
Is set to 0, and during this time, the selecting means is prevented from accessing the subsequent request, and when the processing of the preceding request is completed, it is reset to "0" and the selecting means is allowed to access the subsequent request. The flag means and the output of the inhibition flag means are enabled when the request processing section is operated in a low load environment, and the output of the inhibition flag means is allowed when the request processing section is allowed to operate in a high load environment. And a suppression effective / ineffective control means for controlling so as to be ineffective.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. 1 in the figure
Is a device A request reception buffer that receives a request from device A, 2 is a device B request reception buffer that receives a request from device B, 3 is a device C request reception buffer that receives a request from device C, and 4 is a device A request reception Device A for receiving the output of buffer 1
A buffer read register, 5 is a device B buffer read register that receives the output of the device B request reception buffer 2, 6 is a device C buffer read register that receives the output of the device C request reception buffer 3, and 7 is the buffer read registers 4, 5, A selector that selects three outputs of 6 and outputs them to the request processing unit 10, and 8 is an inter-device priority F / F
The output is input to the busy check circuit 9 and the priority can be changed by the output c of the busy check circuit 9.

Reference numeral 15 is a subsequent request suppression device, which is actually composed of a 1-bit flip-flop. This flip-flop has a function of suppressing the requests existing in the buffer read registers 4, 5, and 6 from entering the request processing unit 10 when the output is "1".
It can be disabled by 16 output states. The flip-flop 15 is a buffer read register 4, 5,
One of the requests in 6 enters the request processing unit 10 and is set by the inhibition set signal g, and is reset by the inhibition release signal i which is a steady signal of the request processing unit 10. Reference numeral 16 denotes a suppression valid flag generator, which controls the validity / invalidity of the output of the subsequent request suppression device 15, and is actually composed of a 1-bit flip-flop. When the output is "1", the subsequent request suppression device 15
Output is enabled, and when it is "0", subsequent request suppression device
Disable the output of 15. 17 is an AND gate.

Reference numeral 9 denotes each bit signal d indicating the request type of the buffer read registers 4, 5, and 6, an output signal of the inter-device priority F / F8, a busy signal b of the request processing unit 10, and a continuous request inhibition signal of the AND gate 17 output. It is a busy check circuit for inputting h, determining a busy state every clock, and supplying one request to the request processing unit 10 through the selector 7. Reference numeral 10 denotes a request processing unit having the buffer of the main memory circuit 11 therein, and the request reception port unit 1
Processes the request input from 6 to 6 through the selector 7, generates the MMU access signal e when the data is not registered in the buffer, and follows the suppression release signal i indicating that the request is not inside. Outputs to request suppression device 15 and cancels suppression.

11 is a main storage device (MM) connected to the request processing unit 10.
U), which is composed of multiple banks with interleaved structure. Reference numeral 12 denotes an apparatus A reply register that receives the output of the request processing unit 10 and outputs reply data to the apparatus A that is the request requesting source. Similarly, a device B reply register 14 for outputting data is a device C reply register for receiving the output of the request processing unit 10 and outputting reply data to the device C which is the request request source. In this case, device A,
B and C correspond to I / O processors, arithmetic processing units, and the like. The requests entered in the request processing unit 10 are designed to obtain the same result as when they are sequentially processed in the order of entry.

As described above, when the output of the suppression valid flag generator 16 is set to "0", the same operation as the conventional one is performed, and when it is set to "1", the logical error avoidance mode is set, and the request processing unit 10 makes one request. Until the processing is completed, the next request is made to wait in the ports 1 to 6. That is, the request processing unit 10 can perform request processing while avoiding complicated processing.

To describe this in detail, it is assumed that the main memory device 11 is composed of eight banks, bank 0 to bank 7, with a bank cycle time of 10T, as described above.
In this case, the present invention, for example, when a request accesses bank 0, suppresses the access of subsequent requests even if it is a different bank. That is, bank n (0 ≦ n ≦ 7)
If a subsequent request occurs in a bank different from the bank n, the subsequent request is suppressed until the access to the bank n is completed (that is, the read and write processing for the bank n is completed). is there. As a result, there is no access to one bank with the same clock. This is called a low load environment. Here, the usage rate of the main storage device 11 is reduced. By constructing this low-load environment, it becomes possible to avoid a logic error that occurs only in a high-load environment.

〔The invention's effect〕

As described above, the memory control device according to the present invention is
Suppression flag means that suppresses access to all subsequent requests and suppression enable / disable that controls validity / invalidity
By providing the invalidation control means, the request processing unit responds to accesses from a plurality of processing devices every clock,
The busy check of the main memory bank is performed to eliminate the high load environment where continuous processing is performed, and the request processing unit processes requests serially, so that it occurs only at critical timing in the high load environment. This has the effect of avoiding an error (logic error) caused by a logic design mistake in a simple LSI.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 1,2,3 …… Request acceptance buffer, 4,5,6 …… Buffer read register, 7 …… Selector, 8 …… Device priority
F / F, 9 ... Busy check circuit, 10 ... Request processing unit, 11 ... Main memory (MMU), 12, 13, 14 ... Reply register, 15 ... Subsequent request suppression device, 16 ...
Suppression valid flag generator, 17 ... AND gate.

Claims (1)

[Claims] 1. A request processing unit (1) having a request receiving port unit (1,2,3,4,5,6) for receiving a request from each input device (A, B, C), and processing a request. Ten)
Means for selecting and outputting one of the requests according to the busy status of the above and the determination result of the priority between the input devices (7,
9), when the processing of the preceding request is started by the selective output of the request, it is set to "1", during which the selecting means is prevented from accessing the subsequent request, and when the processing of the preceding request is completed. A reset flag means (15) that is reset to "0" and permits the selection means to access subsequent requests, and an output of the inhibition flag means when the request processing unit is operated in a low load environment And a suppression enable / disable control means (16, 17) for controlling to disable the output of the suppression flag means when the request processing unit is allowed to operate in a high load environment. And a memory control device.