JP3408262B2 - Digital circuit and method of accessing digital circuit with external elements - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit which enables a CPU core to access an internal memory at a higher speed, and an access to an external element of the digital circuit.
In particular, a digital signal processor (DSP) of a test device for various electric parts such as an IC tester.
D for image processing and audio processing of general-purpose computer
Digital IC and the IC is used as an SP, etc.
Of the external device of the present invention .

[0002]

BACKGROUND ART When a microprocessor accesses a memory, it outputs a desired address on an address bus, and the data (operand, program data, data to be operated, etc.) stored at the address of the memory. ) Is taken in via the data bus. Then, if necessary, the fetched data is stored in a register, and processing such as calculation is performed. In order for the microprocessor to operate at high speed, not only the microprocessor itself operates at high speed, but also the memory access time and the propagation delay time of the signal on the address bus and data bus, It is necessary to reduce the time required for a series of loops such as (output) → (memory data access) → (memory data output) → (data acquisition by MPU).

For this reason, in systems such as IC testers and engineering work stations (EWS),
A digital IC specially designed for the above processing, etc., in which a CPU core and a memory are built in one chip in order to perform high speed Fourier transform, image / audio signal processing, etc. at high speed.
Is also being developed. In such an IC, as shown in FIG. 2, the microprocessor (CPU core 11) and the internal memory 2 are connected via a dedicated memory access bus 5, and the CPU core 11 and the internal memory 2 are connected. To improve the data transfer rate. By the way, when an external element such as a host computer, an I / O port, or an external memory (hereinafter simply referred to as “external element”) accesses the on-chip memory, data by direct memory access (DMA) is used. Transfer is done.

FIG. 3 is an explanatory diagram of a conventional DMA data transfer system showing a state in which a DMA controller 13 is connected to a digital IC 20 having a CPU core 11 and a memory 2 built therein. In the figure, one port P ₁ of the CPU core 11 and the internal memory 2 are connected by the memory access bus 5 as in the case of FIG. 2, and the external system bus 7 is connected via the DMA controller 13. It is connected to the memory access bus 5. Also, CPU core 1
1 originally has a function of accessing the outside, such as an internal register and a cache memory, so that the external system bus 6 is a port P ₂ different from the port P ₁ to which the internal memory 2 of the CPU core 11 is connected. It is connected to the.

In such a digital IC 20, the CP
During the original operation in which the U core 11 operates in combination with the internal memory 2, the DMA controller 13 operates as the CPU core 11
The enable signal (EN) is output to the output, the output of the data and address connected to the CPU core 11 is enabled, and the output of the DMA controller 13 becomes indefinite (tristate state). Conversely, when the external element accesses the internal memory 2, the CPU core 11 outputs the enable signal (EN) to the DMA controller 13, the output of the DMA controller 13 is enabled, and the data and address of the CPU core 11 are transferred. The output is tri-stated. That is, the DMA controller 13 can execute DMA between the external element and the internal memory 2 via the I / O port 7 when there is a DMA request. Further, the CPU core 11 can access the internal memory at a high speed to some extent, and can access the external memory through the I / O port 7.

However, the digital IC 20 shown in FIG.
Then, the memory access bus 5 is connected to the CPU core 11 and the D
Since it is shared with the MA controller 13, the bus length becomes long, the address output load of the CPU core 11 becomes heavy (that is, the load current increases), and the data or address propagation delay time becomes long. However, there is an inconvenience that the access speed to the internal memory 2 is reduced. As described above, when the DMA controller 13 is configured as a separate element from the digital IC 20, the routing of a bus such as an address bus becomes long. However, even if the DMA controller 13 is built in the digital IC 20, the bus is a memory and a CPU. It also becomes a limitation when the distance from the core 11 is made the shortest, and the inconvenience of increasing the propagation delay time of the address cannot be eliminated, and the original CPU operating speed is reduced.

[0007]

An object of the present invention is to provide a CPU which is required to operate at high speed.
Provided is a digital circuit (especially a digital IC) having a core and a memory therein, in which the distance between the CPU core and the built-in memory is minimized and a further high speed operation is achieved, and an access method to an external element of the IC. The purpose is to

[0008]

SUMMARY OF THE INVENTION The present invention will be described below by taking a digital IC as an example. In the present invention, the digital IC has a CPU core having a plurality of ports connected to each other by an internal path, and an internal memory connected to one of the plurality of ports via a memory access bus. ing. And I / O port of digital IC,
A DMA controller is provided on an internal system bus formed between the internal memory and a port other than the port to which the internal memory is connected.

Further, (i) the I / O port and the D
Between the port to which the MA controller is connected, or (ii) between the I / O port and a port other than the port to which the DMA controller or the internal memory is connected among the plurality of ports of the CPU core, A tri-state buffer is provided on the internal system bus formed in. For example, when an external device requests the DMA controller to perform DMA with the internal memory of the digital IC, the DMA controller is controlled by the tri-state
By outputting a use disapproval signal to the buffer, the CP
Disconnect the U core from the external system bus. With this,
The DMA controller outputs an internal logic stop signal (inhibit signal) to the CPU core to stop the internal function of the CPU core. As a result, the external element is
O port, CPU to which the DMA controller is connected
CPU to which the core port and the internal memory are connected
The internal memory can be accessed via the port of the core.

On the other hand, for example, when there is no DMA request from an external element, the DMA controller outputs a use permission signal to the tri-state buffer. In this case, it goes without saying that the DMA controller does not output the internal logic stop signal to the CPU core. As a result, the external element reads data such as a register of the CPU core through the I / O port and the port of the CPU core to which the tri-state buffer is connected, and conversely, the CPU core is an external element. You can read the data from.

[0011]

FIG. 1 is an explanatory view showing an embodiment of the present invention. In the figure, a digital IC 10 is composed of a CPU core 1, an internal memory (which may be RAM, ROM or both of them) 2, a DMA controller 3, and a circuit element of a tri-state buffer 4. . Here, the port P1 of the CPU core 1 and the internal memory 2 are connected by a bus 5 for memory access (composed of an address bus, a data bus, and a control signal line). Further, the external system bus 6 is connected to the I / O port (only one port is shown) 7 of the digital IC 10, and the I / O port and the port P2 of the CPU core 1 have two paths of the internal system bus 8a and 8b
Connected by. That is, one internal system bus 8a is connected to a port via the DMA controller 3.
The other internal system bus 8b is connected to the port P2 via the tri-state buffer 4. Furthermore,
The ports 1 and 2 are connected by the internal path 9 of the CPU core 1. In the figure, the port to which the DMA controller 3 is connected and the tri-state
Although the same port P2 is used as the port to which the buffer 4 is connected, a different port can be used.

On the other hand, the DMA controller 3 tries to
Enable signal (EN) for state buffer 4
A control line for outputting is connected. In FIG.
For convenience of explanation, only the above configuration is illustrated, but various timers such as a watchdog timer, an A / D converter, a port 1,
Ports other than 2, etc., can be incorporated with various devices mounted on a normal DSP or a single-chip microcomputer.

The operation of the digital IC 10 shown in FIG. 1 will be described below. (1) When the DMA controller 3 performs the DMA operation The operation of the DMA controller 3 is the same as the general DMA control. Initialization of the DMA controller 3 is normally performed by setting various registers (address register, counter register, control register) by a host CPU (not shown), another CPU, or the CPU core 1. When the DMA controller 3 receives a DMA request (DMAREQ) from an external element such as the host CPU or another CPU via the external system bus 6, the DMA controller 3 sends an inhibit signal to the CPU core 1 to send a try signal. The non-enable signal is output to the state buffer 4. As a result, the internal function of the CPU core 1 is stopped, and the tri-state buffer 4 is deactivated (undefined from the external logic). Then, the DMA controller 3 or an external element (or, in some cases, the CPU core 1 itself) such as a host CPU or another CPU activates the ports 1 and 2 of the CPU core 1 to transfer the DMA transfer method. DMA transfer according to (burst method, cycle steal method, etc.) is executed. In this case, the external system bus 6 is connected to the memory access bus 5 via the I / O port 7, the DMA controller 3, the port 2, the internal path 9 and the port 1, and has a predetermined address requested by the internal memory 2. Reading and writing of data is performed.

(2) When the DMA controller 3 does not perform the DMA operation In this case, the DMA controller 3 outputs the enable signal (EN) to the tri-state buffer 4,
Tri-state buffer 4 is active and D
The MA controller 3 is inactive by itself. Further, since the inhibit signal is not input to the CPU core 1, the internal logic does not stop. Therefore, the CPU core 1
Can access the external device, the external device through the I / O port 7, the tri-state buffer 4, and the port P ₂ , and also access the internal memory 2. The CPU core 1 accesses the internal memory 2 by starting the memory access bus 5 connected to the port 1. However, since the DMA controller 3 is not connected to the bus, the output of the CPU core 1 is It doesn't get heavy. As described above, the digital IC 10 of the present invention can be manufactured by forming an IC logic on a wafer by a process such as photolithography, etching and ion implantation, or using a gate array or the like. It can also be manufactured. Although the digital IC has been described above, the circuit of the present invention can be formed on a board. In this case, the tri-state buffer 4 can be built in the DMA controller 3.

[0015]

According to the present invention , since the digital circuit does not share the memory access bus between the CPU core and the DMA controller, the length of the system bus itself can be shortened. Therefore, the load of address output of the CPU core becomes heavy, and the inconvenience that the propagation delay time of data and address becomes long does not occur. Further, since the DMA controller can be built in the digital IC, there is no inconvenience that the routing of the bus such as the address bus becomes long. As a result, the access speed to the memory by the CPU core can be further increased.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a digital IC including a CPU core and an internal memory for explaining a conventional technique.

FIG. 3 is an explanatory diagram showing a configuration of a conventional digital IC having a CPU core and an internal memory built therein.

[Explanation of symbols]

1 CPU core 2 internal memory 3 DMA controller 4 tri-state buffer 5 memory access bus 6 external system bus 7 I / O ports 8a, 8b the internal system bus 9 internal path 10 digital IC _{P 1, P} 2 CPU core ports

─────────────────────────────────────────────────── ─── Continued Front Page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 13/28

Claims (2)

(57) [Claims] 1. A digital circuit comprising a CPU core having a plurality of ports, an internal memory connected to one of the plurality of ports via a memory access bus, and an I / O port. Te, said the I / O ports, the internal memory is formed between the ports other than the connection port, the first and second through
An internal system bus 2 path including the road, after the first
The path is equipped with a DMA controller and the second path is
Comprising a line-state buffer, when there is direct memory access i.e. DMA request, the DMA controller is used to output a disable signal to said tri-state buffer, said tri
.From the I / O port via the state buffer
Stop access to the CPU core via the second route
At the same time , it outputs an internal logic stop signal to the CPU core to stop the internal function of the CPU core, and thereby the CPU core port to which the DMA controller is connected and the CPU to which the internal memory is connected. From the I / O port through the core port to the internal
To allow the DMA to the memory, the absence DMA requests, the DMA controller, by outputting a use permission signal to the tri-state buffer, through the tri-state buffer
Digital circuit for the to from the I / O ports allowing access to the CPU core, and wherein the. 2. A CPU core having a plurality of ports, an internal memory connected to one of the plurality of ports via a memory access bus, and an I / O port.
Access from the I / O port of the digital circuit
A method, said I / O port and the internal memory is formed between the ports other than the connection port, the first and second paths
An internal system bus 2 routes including the route of the first
Is equipped with a DMA controller, and a traffic is provided on the second path.
Comprises a Lee-state buffer, when there is direct memory access i.e. DMA request, the DMA controller is used to output a disable signal to said tri-state buffer, said tri
.From the I / O port via the state buffer
Stop access to the CPU core via the second route
At the same time , it outputs an internal logic stop signal to the CPU core to stop the internal function of the CPU core, and thereby the CPU core port to which the DMA controller is connected and the CPU to which the internal memory is connected. From the I / O port through the core port to the internal
To allow the DMA to the memory, the absence DMA requests, the DMA controller, by outputting a use permission signal to the tri-state buffer, through the tri-state buffer
Wherein enabling access from the I / O port to the CPU core, or the I / O ports of the digital circuit, characterized in that it has
Et access methods.