JP3868316B2 - Multiprocessor and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention belongs to a technical field related to a multiprocessor, a multiprocessor core, and a control method thereof including a plurality of processor cores on one chip and a shared memory accessible from the processor core.
[0002]
[Prior art]
In recent years, with the progress of process miniaturization and the demand for higher performance of LSIs, many multiprocessors having a plurality of processor cores mounted on one chip have been developed. Also, from the viewpoint of cost, a multiprocessor capable of realizing a system constituted by a plurality of chips on one chip has been in the spotlight.
[0003]
In such a multiprocessor, when each processor can operate independently, it is possible to easily achieve the maximum performance. However, when it is necessary to exchange data between processor cores on one chip, it is temporarily out of the chip. If the other processor core attempts to send data to the other processor core, the effect mounted on the same chip cannot be obtained. In other words, the data transfer is equivalent to the case of the conventional separate chip configuration.
[0004]
Therefore, conventionally, for example, as disclosed in JP-A-7-105146 or JP-A-5-210640, the above-mentioned problem is solved by providing a shared memory accessible from a plurality of processor cores on one chip. It has been proposed. That is, data created by a certain processor core is stored in the shared memory, and then the processor core that needs this data accesses the shared memory. In this way, since the built-in memory is generally high-speed, it is possible to dramatically improve the transfer efficiency with respect to data transfer compared to the conventional case.
[0005]
[Problems to be solved by the invention]
However, in the conventional device, in order to appropriately perform access requests from processor cores that operate independently from each other, an arbitration circuit is separately required, or a dual-port memory that allows a plurality of accesses must be used as a shared memory. There was a problem that there was.
[0006]
In addition, the dual port memory or the arbitration circuit that avoids complicated contention tends to be large-scale, and there is a problem that it is overspecial except when data exchange between processor cores occurs completely at random. there were.
[0007]
Furthermore, in a general development method of mounting a plurality of processor cores that have already been developed, it is necessary to newly add a design such as an arbitration circuit, which increases the design period.
[0008]
The present invention has been made in view of such various points, and an object of the present invention is to provide a multiprocessor that uses a conventional processor core almost as it is and does not cause contention in a shared memory despite its simple configuration. And
[0009]
[Means for Solving the Problems]
To achieve the above object, according to the first aspect of the present invention, in a multiprocessor having a plurality of processor cores on one chip and a shared memory accessible from the processor core, a memory selection flag writable by a program. A storage means for storing a signal; a switching means for switching and outputting a memory selection flag signal and an external flag signal from the storage means; and when the storage means is read by a program, the output of the switching means is sent to a data bus A driver with control, and a memory control unit that outputs an output of the switching means and a memory access address and outputs a memory access signal to the outside, and is connected to the data bus, the external flag signal, and the switching A plurality of processors receiving an external selection signal for controlling the means; Comprising a core and enter the plurality of memory access signal, and a shared memory connected by a plurality of said data bus in relation to the memory access signal.
[0010]
According to the above configuration, immediately after resetting, the memory control circuit in the processor core does not simultaneously activate the memory access signals for the shared memory, and contention can be avoided. Therefore, when connecting multiple processor cores on a chip, it is possible to easily implement exclusive control to the shared memory, and whether each processor core is permitted to access the shared memory using an internal program. It is easy to know.
[0011]
According to a second aspect of the present invention, a plurality of processor cores provided on one chip and capable of accessing a common memory, storing a memory selection flag signal writable by a program, and memory selection from the storage means Switching means for switching and outputting a flag signal and an external flag signal, a driver with control for sending the output of the switching means to a data bus when the storage means is read by a program, an output of the switching means and a memory access address And a memory control unit that outputs a memory access signal to the outside, and is connected to the data bus and receives the external flag signal and a selection signal for controlling the switching means from the outside. When the selection flag signal is read by a program, the memory selection flag The signal to be transmitted to the data bus.
[0012]
According to the above configuration, when a plurality of processor cores are connected on one chip, it is possible to easily realize exclusive control to the shared memory and whether or not access to the shared memory is permitted. Can easily know.
[0013]
According to a third aspect of the present invention, there is provided a multiprocessor using the multiprocessor core according to the second aspect, wherein the first processor core and the second processor core are mounted, and the selection signal of the first processor core is fixed. The first processor core switching means output signal is logically inverted and applied as an external flag signal of the second processor core, the memory access signal of the first processor core is connected to the shared memory, and A data bus of a first processor core is connected to the shared memory, an external flag signal of the first processor core is fixed, and a selection signal of the second processor core is used as a selection signal of the first processor core. Is fixed with a logically inverted value, the switching means output signal of the second processor core is opened, and the second processor core Connect the re access signal to said shared memory, comprising the data bus of the second processor core to be connected to the shared memory.
[0014]
According to the above configuration, immediately after the reset, the shared memory can be accessed from the second processor core. By reading the selection signal, the program operates as the master side or as the slave side. It is possible to judge whether In the normal operation, when it is necessary to access the shared memory on the first processor core side, the memory control circuit is activated through the data bus. At the same time, the memory control circuit is disabled on the second processor core side. Therefore, the shared memory is connected to the first processor core side, and contention can be avoided. Further, by reading the internal register, it is possible to know the values of the selection signals, and further know whether they are the master side or the slave side. Similarly, by reading the internal register, it is possible to know whether or not the shared memory can be accessed regardless of whether the multiprocessor core is set by itself or due to the influence of the other. Therefore, by considering a few logic circuits, it is possible to obtain a suitable multiprocessor capable of effectively obtaining the effects of the present invention.
[0015]
In a multiprocessor control method according to a fourth aspect of the present invention, the first and second processor cores are simultaneously interrupted using the multiprocessor of the third aspect, and the processor core side having no access right to the shared memory is interrupted. In the routine, access to the shared memory is prohibited, and the other processor core side includes a step of changing the connection destination of the shared memory by switching the storage means by a program. According to a fifth aspect of the present invention, there is provided a multiprocessor control method according to the third aspect, wherein the processor core on the multiprocessor uses the multiprocessor of claim 3 to output the memory selection flag signal from the switching means as the master side. Only when the shared memory is to be accessed by the side processor core, the step of updating the memory selection flag signal by the program to control access to the shared memory is included.
[0016]
According to the above configuration, the first processor core rewrites the storage means while the second processor core is accessing the shared memory, so that the shared memory does not try to belong to the first processor core side. Can do.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the overall configuration of a multiprocessor 1 according to an embodiment of the present invention. In this multiprocessor 1, an identical first processor core 100 and second processor core 200 are provided on one chip. .
[0018]
The processor cores 100 and 200 are connected to the shared memory 300 by respective data buses 110 and 210. In addition, although not shown in the figure, access addresses and control signals are actually output from the respective processor cores 100 and 200.
[0019]
The shared memory 300 performs data transfer with the first processor core 100 through the data bus 110 when the memory access signal 120 coming from the first processor core 100 is active (= “1”). Similarly, the shared memory 300 performs data transfer with the second processor core 200 through the data bus 210 when the memory access signal 220 coming from the second processor core 200 is active (= “1”).
[0020]
The storage circuits 130 and 230 in the processor cores 100 and 200 are storage means for storing memory selection flag signals 170 and 270 that can be written by programs in the processor cores 100 and 200, respectively. When 270 is “1”, the shared memory 300 is selected.
[0021]
The switching means 140 and 240 in the processor cores 100 and 200 switch and output the memory selection flag signals 170 and 270 of the storage circuits 130 and 230 and the external flag signals 150 and 250 inputted from the outside. The selection signals 160 and 260 for controlling the switching means 140 and 240 are received from the outside. When the selection signal 160 is “1”, the output of the storage circuit 130 is adopted as the memory selection flag signal 170, while the selection signal When 260 is “1”, the output of the memory circuit 230 is adopted as the memory selection flag signal 270.
[0022]
Further, the memory selection flag bus output drivers 190 and 290 as output drivers with control send data to the data buses 110 and 210 when the values of the memory selection flag signals 170 and 270 are read by a program. At the same time, the selection signal bus output drivers 191 and 291 as output drivers with control similarly transmit data through the data buses 110 and 210 when reading the values of the selection signals 160 and 260.
[0023]
Then, the memory control circuits 180 and 280 as the memory control unit output the memory access signals 120 and 220 to the outside by inputting the memory selection flag signals 170 and 270 and the memory access address which are the outputs of the switching means 140 and 240, respectively. When the memory selection flag signals 170 and 270 are active (= “1”) and the memory access address is an address indicating the shared memory 300, the memory access signals 120 and 220 are output. The memory access signals 120 and 220 are input to the shared memory 300.
[0024]
The processor cores 100 and 200 described above are connected as follows. That is, the memory selection flag signal 170 that is the output signal of the first processor core 100 is logically inverted and input as the external flag signal 250 of the second processor core 200.
[0025]
The selection signal 160 of the first processor core 100 is fixed to “1”, and similarly, the selection signal 260 of the second processor core 200 is fixed to “0”. The external flag signal 150 of the first processor core 100 is set to a fixed value outside. Since this signal is not selected by the switching means 140, any value may be used as long as it is a fixed value. The memory selection flag signal 270 of the second processor core 200 is opened outside.
[0026]
The memory control circuits 180 and 280 perform memory access when the memory selection flag signals 170 and 270 are active (= “1”) and the memory access address (not shown) is in a range indicating the shared memory 300. The signals 120 and 220 are active (= “1”).
[0027]
The shared memory 300 performs data transfer through the data buses 110 and 210 in response to read / write signals (not shown) coming from the processor cores 100 and 200. It is assumed that the processor cores 100 and 200 have an exception processing function or the like generally possessed by a normal processor core.
[0028]
The operation of the multiprocessor 1 according to the embodiment of the present invention configured as described above will be described. Assume that the memory space of the processor cores 100 and 200 is, for example, a 64K word space, and the shared memory 300 is allocated from the address E000 to the address FFFF.
[0029]
Immediately after the reset, the memory circuit 130 is initialized to “0”. Since the selection signal 160 is fixed (= “1”), the memory selection flag signal 170 is “0”. Accordingly, when the first processor core 100 reads the memory selection flag signal 170, the memory selection flag signal 170 becomes “0”, and the shared memory 300 cannot be selected.
[0030]
Similarly, when the memory selection flag signal 270 is read by the second processor core 200, the selection signal 260 is fixed (= “0”), so the value of the memory selection flag signal 270 is “1” regardless of the value of the storage circuit 230. Thus, if the access address is between E000 and FFFF as memory access, the memory control circuit 280 outputs a memory access signal 220 (= “1”) to the shared memory 300.
[0031]
That is, immediately after the reset, the shared memory 300 can be accessed from the second processor core 200. Then, by reading the selection signals 160 and 260, it is possible to determine whether the program is operating as the master side or the slave side according to the program.
[0032]
During normal operation, when it is necessary to access the shared memory 300 on the first processor core 100 side, “1” is written to the storage circuit 130 through the data bus 110. Since the selection signal 160 is “1”, the memory selection flag signal 170 becomes “1”, and the memory control circuit 180 is activated. At the same time, since the memory selection flag signal 270 becomes “0” on the second processor core 200 side, the memory control circuit 280 is disabled. Therefore, the shared memory 300 is connected to the first processor core 100 side.
[0033]
Therefore, according to the multiprocessor 1 according to the embodiment of the present invention, the memory control circuits 180 and 280 in the processor cores 100 and 200 do not simultaneously activate the memory access signals 120 and 220 for the shared memory 300. Can avoid conflicts.
[0034]
Further, by reading the internal register, the values of the selection signals 160 and 260 can be known, and further, it can be known whether they are the master side or the slave side. Similarly, by reading the internal register, it is possible to know whether each of the processor cores 100 and 200 can access the shared memory 300 regardless of whether it is set by itself or from the other influence. It is.
[0035]
In the above-described embodiment, the principle of exclusive control has been described. In practice, the first processor core 100 rewrites the storage circuit 130 while the second processor core 200 is accessing the shared memory 300. Therefore, it can be considered that the shared memory 300 belongs to the first processor core 100 side.
[0036]
In such a case, as shown in FIG. 2, the first and second processor cores 100 and 200 are interrupted at the same time, and the second processor core 200 side having no access right to the shared memory 300 is in the interrupt routine. A multiprocessor control method including a step of prohibiting access to the shared memory 300 and changing the connection destination of the shared memory 300 by switching the storage circuit 130 by a program on the other first processor core 100 side may be adopted.
[0037]
Alternatively, as shown in FIG. 3, when a write access to the storage circuit 130 on the multiprocessor 1 occurs, the first processor core 100 that outputs a signal output indicating the same is set as the master side, and its memory selection flag signal 170, the second processor core 200 side is stalled, and only when the first processor core 100 tries to access the shared memory 300, the program updates the memory selection flag signal 170 to access the shared memory 300. A multiprocessor control method including the step of controlling
[0038]
In the system in which the access timing can be adjusted, the present invention can be sufficiently applied to a shared memory that is randomly accessed from two processor cores by considering the timing to some extent. .
[0039]
【The invention's effect】
As described above, according to the present invention, when a plurality of processor cores are connected on a chip, exclusive control to the shared memory can be easily realized by considering a few logic circuits, and Each processor core can easily know whether or not access to the shared memory is permitted by an internal program.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a multiprocessor according to an embodiment of the present invention.
FIG. 2 is a diagram showing a control flow of a processor core on a multiprocessor.
FIG. 3 is a view corresponding to FIG. 2 showing a control flow of a processor core on another multiprocessor;
[Explanation of symbols]
1 Multiprocessor 100, 200 Processor core 110, 210 Data bus 120, 220 Memory access signal 130, 230 Storage circuit (storage means)
140, 240 Switching means 150, 250 External flag signal 160, 260 Selection signal 170, 270 Memory selection flag signal 180, 280 Memory control circuit (memory control unit)
190,290 Memory selection flag bus output driver (driver with control)
191,291 Selection signal bus output driver (driver with control)
300 shared memory

Claims (4)

In a multiprocessor having a plurality of processor cores on one chip and a shared memory accessible from the plurality of processor cores,
Each said processor core is
A memory means for storing a memory selection flag signal writable by a program, and outputting the memory selection flag signal to the outside;
Switching means for switching and outputting a memory selection flag signal and an external flag signal from the storage means;
A driver with control for sending the output of the switching means to a data bus when the storage means is read by a program;
A memory control unit that outputs an output of the switching means and a memory access address and outputs a memory access signal to the outside;
The shared memory inputs a plurality of memory access signals, and is connected by a plurality of the data buses in relation to the memory access signals ,
The memory selection flag signal output from the storage means of one processor core of the plurality of processor cores is input as the external flag signal directly or via a logic circuit by at least one processor core other than the processor core. A multiprocessor characterized by: In a multiprocessor having first and second processor cores on one chip and a shared memory accessible from the first and second processor cores,
The first and second processor cores are respectively
A memory means for storing a memory selection flag signal writable by a program, and outputting the memory selection flag signal to the outside;
Switching means for switching and outputting a memory selection flag signal and an external flag signal from the storage means;
A driver with control for sending the output of the switching means to a data bus when the storage means is read by a program;
A memory control unit for outputting a memory access signal to the outside with the output of the switching means and the memory access address as inputs;
While receiving the external flag signal connected to the data bus and a selection signal for controlling the switching means,
When the memory selection flag signal is read by a program, the memory selection flag signal is sent to the data bus ,
Fixing the selection signal of the first processor core;
The first processor core switching means output signal is logically inverted and applied as an external flag signal of the second processor core,
Connecting the memory access signal of the first processor core to the shared memory;
Connecting the data bus of the first processor core to the shared memory;
Fixing an external flag signal of the first processor core;
Fixing the selection signal of the second processor core to a value obtained by logically inverting the selection signal of the first processor core;
The switching means output signal of the second processor core is opened,
Connecting the memory access signal of the second processor core to the shared memory;
A multiprocessor, wherein the data bus of the second processor core is connected to the shared memory. A multiprocessor control method using the multiprocessor of claim 2 to avoid contention in a shared memory,
Interrupt the first and second processor cores simultaneously,
The processor core side that does not have access rights to the shared memory prohibits access to the shared memory in an interrupt routine,
A multiprocessor control method including a step of changing a connection destination of the shared memory by switching a storage unit by a program on the other processor core side. A multiprocessor control method using the multiprocessor of claim 2 to avoid contention in a shared memory,
The side that uses the memory selection flag signal as the output of the switching means in the processor core on the multiprocessor is the master side,
A multiprocessor control method comprising a step of updating a memory selection flag signal by a program to control access to the shared memory only when the master processor core tries to access the shared memory.

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