JPH11283362A - Fifo memory control circuit and microprocessor using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a system performance by shortening a data reading time. SOLUTION: This circuit is provided with a dual-port RAM 31, a write address circuit 32 generating a write address based on the write signal to this RAM 31, a read address circuit 33 generating a read address based on a read signal to this RAM 31, an up/down counter 35 which performs count-up operations every time the write signal is applied to the RAM 31 and performs count-down operations every time the read signal is applied to the RAM 31 and a data buss control circuit 36 which outputs the count value of the up/down counter 35 or the readout data from the RAM 31 by selectively changing over them by control signals (CS, CNTS) from a one-chip CPU. Here, the CPU decides the number of data to be outputted from now on based on the count value of the counter from the data buss control circuit 36 to enable data to be read out continuously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a FIFO memory control circuit mounted on various electronic devices and a microprocessor control circuit using the control circuit.

[0002]

2. Description of the Related Art Conventionally, this type of FIFO memory control (F
first-in: First-out (first-in first-out type); one of memory controls for writing and reading data in order, such as in a stack memory of a computer. Memory control circuit 5 for performing control for processing)
As shown in FIG. 4, a k-word dual port RAM 1 as a memory, a write address circuit 2 for generating a write address for the dual port RAM 1, a read address circuit 3 for generating a read address for the dual port RAM 1, Full-empty control circuit 4 indicating the state of valid data in dual port RAM 1 from read address signal (RA) output from read address circuit 3 and write address signal (WA) output from write address circuit 2
Consists of

A reset signal (RESET) is externally connected to the write address circuit 2 for initialization, and a reset signal (RESET) is externally connected to the read address circuit 3 for initialization. ing. The read address signal (RA) is connected to the read address terminal (RA terminal) of the dual port RAM 1, and the write address signal (WA) is connected to the write address terminal (WA terminal) of the dual port RAM 1. I have. Further, the read address signal (RA) and the write address signal (W
A) is connected to the Full-Empty control circuit 4.

[0004] From the Full-Empty control circuit 4,
The write address signal (W
A), read address signal (RA) of read address circuit 3
A full signal (Full) indicating the state of valid data in the dual port RAM 1 and an empty signal (Em) based on the
pty) is output to the outside. This full signal (Fu
11) is output when the dual-port RAM 1 is full, and the empty signal (Empty) is output when the dual-port RAM 1 is empty. Specifically, the full signal (Full) is asserted when k words of data are written to the dual port RAM1, and the empty signal (Empty) is asserted when 0 words of data are written to the dual port RAM1. Is done.

An externally input FIFO memory write signal (WR) is applied to a write terminal (W) of the dual port RAM 1.
R terminal) and the write address circuit 2. Also, an externally input Fifo memory read signal (R
D) is connected to the read terminal (RD terminal) of the dual port RAM 1 and the read address circuit 3. further,
An externally input Fifo memory chip select signal (CS) is connected to a chip select terminal (CS terminal) of the dual port RAM 1.

A data bus 20 for outputting data to the outside is connected to a read data bus terminal (RDATA) of the dual port RAM 1, and a data bus 21 for inputting write data from the outside is connected to the dual port RAM 1.
Are connected to the write data bus terminal (WDATA terminal).

Next, FIG. 5 shows a configuration of a general microprocessor control circuit using the FIFO memory control circuit 5.

The microprocessor control circuit comprises a CP
U (central processing unit) core 11, control ROM (read only memory) 12 storing execution programs and the like, work RAM (random access memory) 13, and I
One-chip CPU (one-chip CP) with built-in I / O port (input / output port) 14 and clock timer interrupt generation circuit
U) 10 is provided. The CPU core 11 and a control RO
The M12, the work RAM 13, the I / O port 14, and the clock timer interrupt generation circuit 15 are connected by a bus line. The output of the clock timer interrupt generation circuit 15 is
It is connected to a timer interrupt terminal (TMINT) of the CPU core 11.

Further, the microprocessor control circuit has
iFo memory control circuit 5, fifo write circuit 16, chip select signal (cs1) for fifo memory control circuit output from fifo write circuit 16, one chip C
AND circuit 18 that receives the chip select signal (CS2) for the Fifo memory control circuit output from the PU 10
Is provided.

The AND circuit 18 is connected to a chip select terminal (CS terminal) of the FIFO memory control circuit 5. The reset signal (RESET) is connected to the one-chip CPU 10 and the reset terminal (RESET terminal) of the FIFO memory control circuit 5.

The data bus 2 of the one-chip CPU 10
0 is the read data bus terminal (RD
ATA terminal) and the FIFO writing circuit 16
Is connected to the write data bus terminal (WDATA terminal) of the FIFO memory control circuit 5.

A data read signal (RD) of the one-chip CPU 10 is connected to an RD terminal of the FIFO memory control circuit 5, and a full signal (Full) and an empty signal (Empty) of the FIFO memory control circuit 5 are one signal, respectively. InP of I / O port 14 of chip CPU 10
ort (n) and InPort (m).
Also, the full signal (Ful) of the Fifo memory control circuit 5
1) is connected to the FIFO writing circuit 16.

The full signal (Full) is asserted when k words of data are written in the dual port RAM 1 of the FIFO memory control circuit 5. The empty signal (Empty) is transmitted to the dual port RA.
It is negated when the data of the 0th word is written to M1, and is asserted when the data of the 0th word is read from the dual port RAM1.

A write signal (WR) output from the FIFO write circuit 16 is connected to a write terminal (WR terminal) of the FIFO memory control circuit 5. The FIFO writing circuit 16 writes data to the FIFO memory control circuit 5 when data to be written to the FIFO memory control circuit 5 exists and the full signal (Full) of the FIFO memory control circuit 5 is negated. It is designed to be written.

Next, the operation of the microprocessor control circuit will be described with reference to FIG. 6 showing the control of the main routine. First, the CPU core 1 of the one-chip CPU 10
1, when power is supplied to the microprocessor control circuit, a reset signal (RESE
T) is asserted, and the one-chip CPU 10
The memory control circuit 5 and the FIFO writing circuit 16 are initialized.

Subsequently, at St2, the reset signal (RESE)
T) is negated, and the one-chip CPU 10
Initializes the FIFO memory control circuit 5 and the FIFO writing circuit 16. Then, at St4, the one-chip CPU 10
Enables the timer interrupt and enters a standby state at St5.

In this state, when a timer interrupt is generated by the clock timer interrupt generation circuit 15 of the one-chip CPU 10 and the timer interrupt terminal (TMINT) is asserted, the one-chip CPU 10 Execute the interrupt processing routine.

In this case, first, the FIFO writing circuit 16
A case where a clock timer interrupt occurs in a state where no data is written in the iFo memory control circuit 5 will be described. The one-chip CPU 10 first receives an empty signal (Emp) from the InPort (n) of the I / O port 14 at St11.
ty) is read, and it is determined at St12 whether the empty signal (Empty) is asserted or negated. In this case, the empty signal (Empt
Since y) is negated, it is determined that there is no data to be read in the FIFO memory control circuit 5, and the process returns to the main routine. That is, the process returns to the standby state shown in FIG.

The FIFO writing circuit 16 has data to be written to the FIFO memory control circuit 5 and has a full signal (F
If (ull) is negated, the data is put on the data bus 21, and the chip select signal (CS1) and the write signal (WR) are asserted. Then, the FIFO memory control circuit 5 writes data to the dual port RAM 1. Subsequently, the FIFO writing circuit 16 outputs the chip select signal (C
S1) and the write signal (WR) are negated. As a result, the address value of the write address circuit 2 of the FIFO memory control circuit 5 is incremented by one. Then, the FIFO memory control circuit 5 negates the empty signal (Empty). By repeating such an operation, the FIFO writing circuit 16 writes j-word data to the FIFO memory control circuit 5. Then, the FIFO memory control circuit 5 asserts a full signal (Full) when there is no more address space for writing data in the dual port RAM 1.

Next, a case where a clock timer interrupt occurs while the FIFO writing circuit 16 has written j-word data into the FIFO memory control circuit 5 will be described. The one-chip CPU 10 first starts the I / O port 14 at St11.
Empty signal (Empt) from InPort (n) of
y), the empty signal (E) is read at St12.
mpty) is asserted or negated. In this case, the empty signal (Empty)
Is negated, so that the process proceeds to St13.

At St13, the one-chip CPU 10
The data read from the Fo memory control circuit 5 is transferred to the work RA
An address (destination address) to be written to M13 is set in a register in the one-chip CPU 10. In this case, the empty signal (Empty) is negated.
Asserts a chip select signal (CS2) and a data read signal (RD).

The FIFO memory control circuit 5 outputs the data in the dual port RAM 1 to the data bus 21. Then, the one-chip CPU 10 reads the data on the data bus 21, negates the chip select signal (CS2) and the data read signal (RD), and the FIFO memory control circuit 5 increments the address value of the read address circuit 3 by +1.

Subsequently, the one-chip CPU 10 is connected to the Fifo
One word data is read from the memory control circuit 5, and the read data is written to the work RAM 13. The above Fifo
The memory control circuit 5 negates a full signal (Full) when an address space for writing data into the dual port RAM 1 is generated, and asserts an empty signal (Empty) when there is no more data in the dual port RAM 1.

Next, the one-chip CPU 10 operates at St15.
In step 16, the destination address is incremented, and in St16, the InPort of the I / O port 14 is used.
The state of the empty signal (Empty) is read from (n).

Subsequently, the one-chip CPU 10 executes St1
At 7, it is determined whether the empty signal (Empty) is asserted or negated. At this time, if the empty signal (Empty) is asserted, F
It is determined that there is no data to be read in the iFo memory control circuit 5, and the process returns to the main routine. That is, the process returns to the standby state shown in FIG. If the empty signal (Empty) is negated in St17, the process returns to St14. By such processing, the one-chip CPU 10
The data of j words in the iFo memory control circuit 5 is completely written in the work RAM 13.

Next, the operation of the one-chip CPU 10 in a machine cycle in the timer interrupt processing routine will be described. In St11, the one-chip CPU 10 fetches the operation code of the instruction for reading the empty signal (Empty), and fetches the operand at the address of the empty signal (Empty). With this, one-chip CPU
10 interprets the above instruction and outputs an empty signal (Empt).
Read y).

At St12, the one-chip CPU 10 fetches the operation code of the instruction for determining the empty signal (Empty), fetches the operand of the instruction for determining the empty signal (Empty), and outputs the empty signal (E
mpty) is asserted or negated. Thereby, when it is determined that the empty signal (Empty) is asserted in St12, the operation code of the instruction to return to the main routine is fetched, and the processing returns to the main routine.

At St13, the one-chip CPU 10 sets Fi
The data read from the Fo memory control circuit 5 is transferred to the work RA
An operation code of an instruction for setting an address (destination address) to be written to M13 in a register in the one-chip CPU 10 is fetched. The data read from the FIFO memory control circuit 5 is stored in the work RAM 13.
Fetches an operand of an instruction for setting an address (destination address) to be written into a register in the one-chip CPU. Thereby, one chip CP
U10 sets an address (destination address) at which data read from the FIFO memory control circuit 5 is written to the work RAM 13 in a register in the one-chip CPU 10.

At St14, the one-chip CPU 10
One word data is read from the Fo memory control circuit 5,
An operation code of an instruction for writing the read data to the work RAM 13 is fetched. Then, the operand of the address of the FIFO memory control circuit 5 is fetched, and the work RA
Fetch the operand at the address of M13. As a result, the one-chip CPU 10 reads out one word of data from the FIFO memory control circuit 5 and writes it into the work RAM 13.

At St15, the one-chip CPU 10 fetches the operation code of the instruction for incrementing the destination address. Thereby, one chip CP
U10 increments the destination address.

At St16, the one-chip CPU 10 fetches the operation code of the instruction for reading the empty signal (Empty) and fetches the operand at the address of the empty signal (Empty). As a result, the one-chip CPU 10 interprets the above-mentioned command and outputs the empty signal (Em).
pty).

At St17, the one-chip CPU 10 fetches the operation code of the instruction for determining the empty signal (Empty) and fetches the operand of the instruction for determining the empty signal (Empty). Thereby, the one-chip CPU 10 determines whether the empty signal (Empty) is asserted or negated.
At this time, if the empty signal (Empty) is negated, it is determined that there is no data to be read in the FIFO memory control circuit 5, and the operation code of the instruction to return to the main routine is fetched. With this, one-chip CPU
10 returns to the main routine. If the empty signal (Empty) is asserted, the process returns to St14.

[0033]

However, such F
In the iFO memory control circuit, a dual port RA
Information on the number of words stored in M1 is stored in one chip C
Since there was no means for the PU to acquire, all data in the dual port RAM 1 was read in the timer interrupt processing routine while checking the empty signal (Empty) every time one word was read. As described above, if the empty signal (Empty) is checked every time one word is read out from the empty signal (Empty), it takes time and there is a problem that the performance of the system is reduced.

In recent years, CPUs have built-in auto-increment and decrement data count registers and use these functions to reduce the operation code fetch and operand fetch. Since the circuit performs processing for checking the empty signal (Empty) every time one word is read, such a function cannot be applied.

Therefore, the present invention provides a dual-port RAM.
The information on the number of words stored in the memory can be output to the outside, and this information is monitored by an external microprocessor. By checking the empty signal (Empty) every time one word is read, a plurality of words can be output. An object of the present invention is to provide a FIFO memory control circuit which can be read out at a time and improve the performance of a system, and a microprocessor control circuit using the control circuit.

[0036]

According to the present invention, there is provided a memory capable of reading and writing data, a write address circuit for generating a write address based on a write signal to the memory, and a memory. And a read address circuit for generating a read address based on a read signal to the memory, the count-up operation is performed each time a write signal is applied to the memory, and the count-up operation is performed each time the read signal is applied to the memory. An up-down counter for performing a count-down operation, and an output control circuit for selectively switching and outputting a count value of the up-down counter and data read from a memory by an external control signal, and providing an output control circuit. Circuit.

According to a second aspect of the present invention, there is provided a memory capable of reading and writing data, a write address circuit for generating a write address based on a write signal to the memory, and a write address circuit based on a read signal to the memory. Memory control circuit having a read address circuit for generating a read address, and a microprocessor for supplying a write signal to the FIFO memory control circuit to write data and supplying the read signal to read the data An up-down counter that performs a count-up operation each time a write signal is supplied to the memory and performs a count-down operation each time a read signal is supplied to the memory; The count value of the up / down counter and the read data from the memory are changed by an external switching control signal. An output control circuit for selectively switching and outputting the data. The microprocessor supplies a switching control signal to the FIFO memory control circuit prior to reading data from the FIFO memory control circuit, and supplies the count value of the up / down counter to the FIFO memory control circuit. Is read out, the number of data to be read out is determined based on the count value, a switching control signal is supplied to the FiFo memory control circuit, and a process for continuously reading out the read out data is performed. This is a microprocessor control device using a memory control circuit.

[0038]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a diagram showing a configuration of a Fifo memory control circuit according to the present invention. The FIFO memory control circuit 30 includes a k-word dual port RAM 31, a write address circuit 32 for generating a write address for the dual port RAM 31, a read address circuit 33 for generating a read address for the dual port RAM 31, and a read address circuit 33. From the read address signal (RA) output from the write address signal (WA) and the write address signal (WA) output from the write address circuit.
The full-empty control circuit 34 indicating the state of valid data in the RAM and the write signal (W
R) is provided, and an up-down counter 35 is provided which performs a count-up operation each time a read signal (RD) is applied to the dual port RAM 31.

The FIFO memory control circuit 30 also includes a data bus 40 for selectively connecting the count value from the output terminal (CNTQ) of the up / down counter 35 and the read data from the dual port RAM 31 to the one-chip CPU 60. And a data bus control circuit 36 for outputting the data to the bus. The data bus control circuit 36 includes a two-input OR gate 37a and a tri-state buffer 37b, and controls a read data output control circuit 37 for controlling the output of the read data from the dual port RAM 31 to the data bus 40. A count value output control circuit 38 is provided for controlling an output to the data bus 40 with respect to the count value of the up / down counter 35 composed of the 38a and the tri-state buffer 38b.

A reset signal (RESET) is externally connected to the write address circuit 32 for initialization, and a reset signal (RESET) is externally connected to the read address circuit 33 for initialization. ing. Also,
A reset signal (RESET) is externally connected to the up / down counter 35 for initialization.

The read address signal (RA) is connected to the read address terminal (RA terminal) of the dual port RAM 31, and the write address signal (WA) is connected to the write address terminal (WA terminal) of the dual port RAM 31. It is connected. Further, the read address signal (RA)
And the write address signal (WA) is Full-Empty.
It is connected to the control circuit 34.

The full-empty control circuit 34 outputs valid data in the dual port RAM 31 based on the write address signal (WA) to the write address circuit 32 and the read address signal (RA) of the read address circuit 33. A full signal (Full) indicating the state and an empty signal (Empty) are output to the outside. This full signal (Full) is output when the dual port RAM 31 is full, and the empty signal (Empty) is
Output when the dual port RAM 31 is empty. Specifically, the full signal (Full) is asserted when k words of data are written in the dual port RAM 31, and the empty signal (Empty) is asserted when 0 words of data are written in the dual port RAM 31. Asserted. The externally input FIFO memory write signal (WR) is connected to the write terminal (WR terminal) of the dual port RAM 31, the write address circuit 32, and the UP terminal of the up / down counter 35. The externally input Fifo memory read signal (RD) is
Read terminal (RD terminal) of dual port RAM 31, read address circuit 33, DO of up / down counter 35
The WN terminal is connected to one input terminal of each of the two-input OR gates 37a and 38a of the data bus control circuit 36.

The externally input Fifo memory chip select signal (CS) is connected to the chip select terminal (CS terminal) of the dual port RAM 31 and the other input terminal of the two-input OR gate 37a of the read data output control circuit 37. . The output of the 2-input OR gate 37a is connected to the control terminal of the tri-state buffer 37b. The input terminal of the tri-state buffer 37b is connected to the read data bus terminal (RD) of the dual port RAM 31, and the output terminal of the tri-state buffer 37b is connected to the data bus 40 output to the outside. .

The up / down counter chip select signal (CNTCS) input from the outside is connected to a two-input OR gate 38a of the count value output control circuit 38. The output of the two-input OR gate 38a is connected to the control terminal of the tristate buffer 38b. The input terminal of the tri-state buffer 38b is connected to the output terminal (CNTQ) of the up / down counter 35, and the output terminal of the tri-state buffer 38b is connected to the data bus 40 that is output to the outside.

Next, FIG. 2 shows the configuration of a general microprocessor control circuit using the FIFO memory control circuit 30. The microprocessor control circuit includes a CP
U (central processing unit) core 61, control ROM (read only memory) 62 storing execution programs and the like, work RAM (random access memory) 63 and I
One-chip CPU (one-chip CP) having a built-in I / O port (input / output port) 64 and a clock timer
U) 60. CPU core 61 and control RO
The M62, the work RAM 63, the I / O port 64, and the clock timer interrupt generation circuit 65 are connected by a bus line. The output of the clock timer interrupt generation circuit 65 is
It is connected to a timer interrupt terminal (TMINT) of the CPU core 61.

The FIFO memory control circuit 30, Fi
Fifo memory writing circuit 6 comprising Fo writing control circuit
6. F output from the FIFO memory write circuit 66
Chip select signal for CS memory control circuit (CS
1) A logical product circuit 68 is provided which receives a chip select signal (CS2) for a FIFO memory control circuit output from the one-chip CPU 60 as an input.

The AND circuit 68 is connected to the chip select terminal (CS terminal) of the FIFO memory control circuit 30. The reset signal (RESET) is connected to the reset terminal (RESET terminal) of the one-chip CPU 60 and the FIFO memory control circuit 30.

The data bus 4 of the one-chip CPU 60
0 is connected to the read data bus terminal (RDATA terminal) of the FiFo memory control circuit 30;
The data bus 41 of the o memory write circuit 66 is connected to the write data bus terminal (WDATA terminal) of the FIFO memory control circuit 30.

The data read signal (RD) of the one-chip CPU 60 is connected to the RD terminal of the FIFO memory control circuit 30, and the full signal (Full) and the empty signal (Empty) of the FIFO memory control circuit 30 are
Each of the I / O ports 64 of the one-chip CPU 60
nPort (n) and InPort (m). In addition, the full signal (F
(ull) is connected to the FIFO writing circuit 66.

The full signal (Full) is asserted when k words of data are written to the dual port RAM 31 of the FIFO memory control circuit 30. The empty signal (Empty) is negated when the data of the 0th word is written to the dual port RAM 31, and is asserted when the data of the 0th word is read from the dual port RAM 31.

The up / down counter chip select signal (CNTC) output from the one-chip CPU 60
S) is connected to the CNTCS terminal of the FIFO memory control circuit 30.

The write signal (WR) output from the FIFO memory write circuit 66 is supplied to the FIFO memory control circuit 3
0 is connected to the write terminal (WR terminal). This Fi
The Fo memory writing circuit 66 includes the Fifo memory control circuit 3
When there is data to be written to 0 and the full signal (Full) of the FIFO memory control circuit 30 is negated, the data is written to the FIFO memory control circuit 30.

Next, the operation of the microprocessor control circuit will be described with reference to FIG. Note that the main routine in the present embodiment is the same as that shown in FIG. 6, and a description of the operation will be omitted.

In the standby state shown in FIG. 6, a timer interrupt is generated by the clock timer interrupt generating circuit 65 of the one-chip CPU 60, and a timer interrupt terminal (TMINT)
Is asserted, the one-chip CPU 60 executes a timer interrupt processing routine as shown in FIG.

In this case, first, the FIFO writing circuit 16
A case where a clock timer interrupt occurs in a state where no data is written in the iFo memory control circuit 10 will be described.
The one-chip CPU 60 first performs ST (step) 11
, The state of the empty signal (Empty) is read from InPort (n) of the I / O port 64, and it is determined in ST12 whether the empty signal (Empty) is asserted or negated. In this case, since the empty signal (Empty) is negated, FiF
o It is determined that there is no data to be read in the memory control circuit 30, and the process returns to the main routine. That is, the process returns to the standby state shown in FIG.

The FiFo memory writing circuit 66 has a Fi
If there is data to be written to the Fo memory control circuit 30 and the full signal (Full) is negated, the data is put on the data bus 21 and the chip select signal (CS1) and the write signal (WR) are asserted. Then, the FIFO memory control circuit 30 writes data to the dual port RAM 31. Subsequently, the FIFO memory write circuit 66 negates the chip select signal (CS1) and the write signal (WR). Thereby, the address value of the write address circuit 32 of the FIFO memory control circuit 30 is incremented by one. Then, the FIFO memory control circuit 30 outputs the empty signal (E
mpty) is negated. By repeating such operations, the FIFO memory writing circuit 66 writes j word data to the FIFO memory control circuit 30. When the address space for writing data in the dual port RAM 31 runs out, the FIFO memory control circuit 30 outputs a full signal (Full signal).
1) is asserted.

Next, the FiFo memory writing circuit 66
A case where a clock timer interrupt occurs while j-word data is written in the Fo memory control circuit 30 will be described. The one-chip CPU 60 first performs I / O in ST11.
The state of the empty signal (Empty) is read from InPort (n) of the port 14, and it is determined in ST12 whether the empty signal (Empty) is asserted or negated. In this case, the empty signal (E
mpty) is negated, and the process proceeds to ST13.

In ST13, one-chip CPU 60 sets Fi
The data read from the Fo memory control circuit 30 is transferred to the work R
An address (destination address) to be written to the AM 62 is set in a register in the one-chip CPU 60. In this case, since the empty signal (Empty) is negated, the process proceeds to ST14.

In ST14, one-chip CPU 60 asserts an up / down counter chip select signal (CNTCS) and a data read signal (RD). Then, in the FIFO memory control circuit 30, the count value of the up / down counter 35 is output to the data bus 40 via the tri-state buffer 38b according to the output of the two-input OR gate 38a of the count value output control circuit 38. Then, the one-chip CPU 60 reads the data on the data bus 40 and sets the data in the auto increment / decrement data count register. In addition, one-chip CP
U60 is an up / down counter chip select signal (C
NTCS) and a data read signal (RD).

In this case, the empty signal (Empty)
Is negated, so that one chip C
The PU 60 asserts a chip select signal (CS) and a data read signal (RD). Then, in the FIFO memory control circuit 30, the read data output control circuit 37
The data in the dual port RAM 1 is output to the data bus 40 via the tri-state buffer 37b according to the output of the input OR gate 37a. And one chip C
The PU 60 reads the data on the data bus 40 and negates the chip select signal (CS) and the data read signal (RD). The FIFO memory control circuit 30 increases the address value of the read address circuit 33 by one.

The one-chip CPU 60 reads one word of data from the FIFO memory control circuit 30 and
Write the read data to M63 and set the value of the auto-increment / decrement data count register to -1.
Then, the value of the destination address register is incremented by one.

The FIFO memory control circuit 30 negates a full signal (Full) when an address space for writing data in the dual port RAM 1 is generated. Then, the process of ST15 is repeated until the value of the auto increment / decrement data count register becomes 0.

Then, the one-chip CPU 60 sets ST
After the end of the process of No. 15, the process returns to the main routine. That is, the process returns to the standby state shown in FIG. Thus, the one-chip CPU 60 finishes writing the j-word data in the FIFO memory control circuit 30 to the work RAM 63.

Next, the operation of the one-chip CPU 60 in the machine cycle in the timer interrupt processing routine will be described. In ST11, the one-chip CPU 60 fetches the operation code of the instruction for reading the empty signal (Empty) and fetches the operand of the address of the empty signal (Empty). With this, one-chip CPU
60 interprets the above command and outputs an empty signal (Empt).
Read y).

In ST12, one-chip CPU 60 fetches the operation code of the instruction for judging empty signal (Empty), fetches the operand of the instruction for judging empty signal (Empty), and outputs empty signal (E).
mpty) is asserted or negated. Thus, when it is determined in ST12 that the empty signal (Empty) is asserted, the operation code of the instruction to return to the main routine is fetched, and the processing returns to the main routine.

In ST13, one-chip CPU 60 sets Fi
The data read from the Fo memory control circuit 30 is transferred to the work R
An operation code of an instruction for setting an address (destination address) to be written to the AM 63 in a register in the one-chip CPU 60 is fetched. Then, the one-chip CPU 60 fetches an operand of an instruction for setting an address (destination address) for writing data read from the FIFO memory control circuit 30 to the work RAM 63 in a register in the one-chip CPU 60. As a result, the one-chip CPU 60 sets an address (destination address) at which data read from the FIFO memory control circuit 30 is written to the work RAM 63 in a register in the one-chip CPU 60.

In ST14, one-chip CPU 60 sets Fi
The operation code of the instruction for reading the count value of the up / down counter 35 of the Fo memory control circuit 30 is fetched, and the operand of the instruction for reading the count value is fetched. As a result, the one-chip CPU 60 reads the value of the up / down counter and sets it in the auto increment / decrement data count register.

In ST15, one-chip CPU 60 sets Fi
One-word data is read from the Fo memory control circuit 30, the read data is written into the work RAM 63, and an operation code of an instruction for decrementing the value of the auto increment / decrement data count register by -1 and incrementing the value of the destination address register by +1 is fetched. And FiF
o Fetch the operand at the address of the memory control circuit 30. As a result, the one-chip CPU 60
One word data is read from the memory control circuit 30, and the read data is written into the work RAM 63. Then, the one-chip CPU 60 increments the destination address, and decrements the auto-increment and decrement data count registers. Such processing of ST15 is repeated until the value of the auto increment / decrement data count register becomes zero.
When the process of ST15 is completed, the one-chip CP
U60 fetches the operation code of the instruction returning to the main routine. Thereby, the one-chip CPU 60 returns to the main routine.

As described above, in the embodiment of the present invention, the count-up operation is performed every time a write signal is applied to dual port RAM 31 in FiFO memory control circuit 60, and a read signal is applied to dual port RAM 31. Up / down counter 35 that performs a countdown operation for each
The count value of the up / down counter 35 is output to the data bus 40 based on the up / down counter chip select signal (CNTCS) from U60, and the one-chip CP
A data bus control circuit for outputting read data from the dual port RAM to the data bus based on a chip select signal (CS) from the U is provided, and the one-chip CPU stores the output from the data bus in the dual port RAM. Since the information of the number of words that have been written can be known, the empty signal (Empty) is not checked every time one word is written.
Multiple words can be read at once.

More specifically, the one-chip CPU 60 accesses the up / down counter 35 to set the value of valid data stored in the dual port RAM 31 in the auto-increment and decrement data count registers of the one-chip CPU 60. Each time one word is read out in the timer interrupt processing routine, the data for that word is collected together without checking the empty signal (Empty).
1 and the number of operation code fetches and operand fetches during data reading can be reduced. As a result, the time required for the data reading process can be reduced, and the performance of the system can be improved.

[0071]

As described above in detail, according to the present invention, an up / down counter which performs a count-up operation each time a write signal is supplied to a memory and performs a count-down operation each time a read signal is supplied to a memory. By providing an output control circuit for selectively switching and outputting the count value of the up / down counter and read data from the memory according to an external control signal, a microprocessor or the like is stored in the memory from the output of the output control circuit. You can know the information of the number of words.

Accordingly, if the microprocessor determines the number of data to be read from now on the basis of the count value of the up / down counter from the output control circuit and continuously reads data by the number of read data, one word can be obtained. It is not necessary to check the empty signal (Empty) every time is read. As a result, the time required for processing for reading data from the memory can be reduced, and the performance of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a FIFO memory control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a general microprocessor control circuit using the FIFO memory control circuit shown in FIG. 1;

FIG. 3 is a flowchart showing a timer interrupt processing routine performed by a one-chip CPU 60 for the microprocessor control circuit shown in FIG. 2;

FIG. 4 is a block diagram showing a configuration of a conventional FIFO memory control circuit.

FIG. 5 is a block diagram showing a configuration of a general microprocessor control circuit using the FIFO memory control circuit shown in FIG. 4;

FIG. 6 is a flowchart showing a main routine of processing performed by a one-chip CPU for the microprocessor control circuit shown in FIG. 5;

7 is a flowchart showing a timer interrupt processing routine performed by a one-chip CPU for the microprocessor control circuit shown in FIG. 5;

[Explanation of symbols]

 Reference Signs List 30 Fifo memory control circuit 31 Dual port RAM 32 Write address circuit 33 Read address circuit 34 Full-Empty control circuit 35 Up-down counter 36 Data bus control circuit 37 Read data output control circuit 38 Count Value output control circuit 40 Data bus 60 One-chip CPU 65 Clock timer interrupt generation circuit 66 FiFO writing circuit

Claims (2)

[Claims] A memory capable of reading and writing data, a write address circuit for generating a write address based on a write signal to the memory, and a read address based on a read signal to the memory An up-down counter for performing a count-up operation each time a write signal is applied to the memory, and performing a count-down operation each time a read signal is applied to the memory;
An fifo memory control circuit, comprising: an output control circuit for selectively switching and outputting a count value of the up / down counter and read data from the memory according to an external control signal. 2. A memory capable of reading and writing data, a write address circuit for generating a write address based on a write signal to the memory, and a read address based on a read signal to the memory And a microprocessor which supplies a write signal to the FIFO memory control circuit to write data and supplies a read signal to read the data. In the processor control circuit, the FIFO memory control circuit performs a count-up operation each time a write signal is supplied to the memory, and performs a count-down operation each time a read signal is supplied to the memory; Switching control signal, the count value of the up / down counter and the readout data from the memory. An output control circuit that selectively switches and outputs the data, the microprocessor supplies a switching control signal to the Fifo memory control circuit before reading data from the Fifo memory control circuit, and A process of reading the count value of the up / down counter, determining the number of data to be read from now on the basis of the count value, supplying a switching control signal to the FIFO memory control circuit, and continuously reading data by the number of read data. F characterized by performing
A microprocessor control device using an iFo memory control circuit.