JPH0424863A - Information processing system - Google Patents

Abstract

PURPOSE:To set the optimum timing for execution of a deadlock interruption by setting freely the initialization value with an instruction for a lock ward access counter of a communication register. CONSTITUTION:A CPU 1-2 produces a test and set instruction in order to have an access to a shared memory 11 while this memory 11 is kept locked by a CPU 1-1. Then the value of a lock word access counter is counted down one by one by a subtractor 6 for the designated word of a communication register 3 every time the reference is given to the register 3 for the lock information on the memory 11. The subtracted value of the counter is sent to a deadlock detection control circuit 7. The circuit 7 detects the deadlock state of the mem ory 11 when the counter value is equal to 0 and reports the lock information on the memory 11 to the CPU that referred to the register 3. Thus this CPU performs a deadlock interruption. As a result, the optimum timing can be set for the deadlock interruption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing system, and particularly to an information processing system related to exclusive control of shared resources in a multiprocessor system, that is, deadlock detection control.

[Conventional technology]

In conventional information processing systems, when multiple processors try to access a shared resource in a multiprocessor system, if simultaneous access between processors would cause a conflict, one processor locks the shared resource and releases it. Up until now, a method has been used to prevent access by other processors, but to achieve this, a communication area is set up in memory, and when a processor attempts to access a shared resource, lock information is sent to the communication area. Another processor that attempts to access the same shared resource will check the communication area before accessing it, and if it is locked, it will wait, and if it is not locked, it will lock itself and access it. I am.

A command called test and set command for accessing the communication area is also supported. A 1-bit flag called a lock flag is provided in the communication area as a means for indicating whether or not the shared resource is locked.
If the lock flag is 1, it is locked, and the lock flag is O
In many cases, this indicates that the lock is not locked. Additionally, some systems have dedicated communication registers and memory that can be accessed at high speed in order to speed up communication between processors. An important problem in communication between these processors is that a processor that has accessed a shared resource while locking it may fall into a deadlock state in which the processor does not release the lock for some reason. Deadlock can be detected by counting the number of accesses of the test and set command under software control, or by initially setting the access count value at lock time and decrementing it by 1 each time the communication area is accessed by the test and set command. , when it becomes 0, a deadlock interrupt is generated and the locked resources are forcibly released. Conventionally, in many systems, only fixed values are set for these count values at the time of locking.

[Problem to be solved by the invention]

Deadlock detection control for shared resources in the conventional multiprocessor system described above is based on an access count value (hereinafter, a counter that counts this value is referred to as a lock word access counter) that is set when a certain processor locks a shared resource. Since the initial value is always constant, regardless of the length of time that a processor actually locks the shared resource, the timing of deadlock interrupts by other processors is constant, and the amount of time that a processor locks the shared resource is fixed. If the initial value is large even though the processor is short, deadlock detection will be delayed; conversely, if the time it takes for the processor to lock the shared resource is long and the initial value is small, the processor will not be able to lock the shared resource. The drawback is that a deadlock interrupt may occur during use.

Also, considering the case where the processor that locks the shared resource is in normal mode and the case where it is in diagnostic mode such as debugging due to instructions from the service processor, if the processor in normal mode locks the shared resource, ,
Since the machine cycle of a processor in the normal mode is fast, as shown in the time chart of FIG. It does not take a long time from the start of reference to the shared resource until the shared resource is unlocked, and therefore, the lock word is accessed by accessing the communication register before the shared resource is unlocked. If the access counter counts down to O and no deadlock interrupt occurs, but a processor in diagnostic mode has locked a shared resource, the machine cycle of the processor in diagnostic mode is the same as the machine cycle of the processor in normal mode. As shown in the time chart of FIG. 5(b), the shared resource is locked after the processor in normal mode starts referencing the communication register in an attempt to access the shared resource. It takes a very long time to unlock the resource, and therefore, even if the initial value of the lock word access counter that is set when the processor in diagnostic mode locks the resource is the maximum value that can be set, the processor in diagnostic mode locks the shared resource. There is a drawback that the lock word access counter counts down to O by an access command to the communication register while resources are in use, causing a deadlock interrupt to the processor in the normal mode.

[Means for Solving the Problems] An information processing system of the present invention includes one or more communication information storages for storing control information and data related to communication between processors in an information processing system constituted by a plurality of processors. means for instructing the communication information storage means to read, store, and inspect; and in response to the instruction means, inspecting the contents of the communication information storage means and, based on the result, reading out, storing, and inspecting the communication information storage means; It has access control means for updating deadlock information, and deadlock detection means for inspecting the deadlock information, detecting the occurrence of deadlock, and reporting it to the processor.

Furthermore, the information processing system of the present invention has one or more mode bits that enable/disable the deadlock detection means to report deadlock to the processor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In FIG. 1, this embodiment is a multiprocessor system consisting of four CPUs 1-1 to 1-4, and also includes a communication register access control circuit 2, 3 communication registers, and two selectors 4-1.
1.4-2.4 registers 5-1.5-2.5-3.
5-4, subtracter 6, deadlock detection circuit 7, decoder 8.4 deadlock interrupt mask circuits 9-1.9-2
．． 9-3.9-4, a service processor 10, and a shared memory 11. The communication register 3 is a register group of 64 bits x 256 words as shown in FIG. 2, and one word is 1 bit 1 . It consists of a 31-bit lock flag, a 31-bit lock word access counter, and a 32-bit communication information area.

Next, the operation of this embodiment will be explained. When CPUl-1 locks the shared memory 11, CPUl-1 locks the shared memory 11 to confirm that the shared memory 11 is currently unlocked.
1 issues an access command (hereinafter referred to as test and set command) to the communication register 3, and stores it in the command register 1-1-1 shown in FIG. test and se
As shown in Figure 4, the software instruction consists of an 8-bit operation code, an 8-bit communication register memory address, and 1.
It consists of a 6-bit address in the CPU register memory, and 63-bit data is read from the address indicated by the test and set instruction in the CPU register group 1-1-2, and the data is accessed to the communication register along with the address in the communication register. The signal is sent to the control circuit 2. CPU
The 63-bit data read from the register group 1-1-2 consists of the initial setting value of the 31-bit lock word access counter written to the communication register 3 and the 32-bit communication information between the processors. The initial values of the counters are set to optimal values by predicting in advance how long a task executed on the CPU that locks the shared resource will use the shared resource, and by analyzing past data. .

Based on the data received from CPU1-1, the communication register access control circuit 2 reads one word of data from the address indicated by the test ant set command in the communication register 3 through the address signal 202, and sets the open/tsuku flag in the word. Confirm that it is O,
The word lock flag is set to 1 through the address signal 202 and write enable signal 203. The selectors 4-1 and 4-2 each receive the initial setting value of the lock word access counter output from the communication register access control circuit 2 in response to the value of the lock flag being 1 when a word is read. and interprocessor communication information. The initial setting value of the selected word/word access counter and the communication information between the processor and the processor are written into the designated area in the lock word. The value of the open/tsuku flag is sent to the decoder 8 together with the identification signal 201 of the CPU that accessed the communication register 3, and the decoder 8
A signal reporting the value of the mouth/tsuku flag is decoded using the identification signal 201 of the PU, and the value of the mouth/tsuku flag is sent to the CPU l.
After receiving the report, the CPU l-1 confirms that the value of the lock flag is 0 and then starts accessing the shared memory 11.

After the shared memory 11 is locked by CPUl-1, CPUl-2 tries to access the shared memory 11 and transfers the lock information regarding the shared memory 11 to the communication register 3.
Go to see. Communication register access control circuit 2 is C
According to the test and set command received from PU1-2, the designated word of the communication register 3 is read out. When the communication register access control circuit 2 confirms that the lock flag in the word is 1, it writes the lock flag to 1 as it is and the communication information to the word through the selector 4-2, writing the read value as it is, and locks the word. As for the word access counter, the subtracter 6 uses the read value through the selector 4-1.
Write the value counted down by 1. The value of the read lock flag is sent to CPU1-2 through decoder 8.
After confirming that the value of the lock flag is 1, the CPU 1-2 enters a state of waiting for access to the shared memory 11. While shared memory 11 is locked by CPUl-1, CPUl-2 locks shared memory 11.
Every time you try to access the communication register 3, issue a test and set instruction, and refer to the lock information regarding the shared memory 11 in the communication register 3, as described above.
The value of the lock word access counter of the specified word in is counted down by 1 by the subtracter 6,
The value is sent to the deadlock detection control circuit 7. The deadlock detection control circuit 7 detects a deadlock state in the shared memory 11 when the value of the lock word access counter becomes O, reports the lock information regarding the shared memory 11 to the CPU that refers to the communication register 3, and receives the report. The deadlocked CPU issues a deadlock interrupt. Note that the CPU
-3, when CPU1-4 attempts to access the shared memory 11, the same thing as above is performed.

As another example, in the same configuration as shown in FIG. 1, the CPU 1-1 is in a diagnostic mode such as debugging due to commands from the service processor 10, and the machine cycle becomes extremely slow, or the instructions are executed sequentially without using the advance control function. If the processing time is long, the service processor 10 sends a deadlock interrupt mask signal to the four deadlock interrupt mask circuits 9-1 to 9-4 in advance before accessing the shared resource, and waits until the signal is received. Deadlock interrupt mask circuit 9-
1 to 9-4 mask the deadlock detection signal received from the deadlock detection control circuit 7. After masking, the deadlock detection signal output from the deadlock detection control circuit 7 is CP even if the value of the lock word access counter becomes O by the test and set instruction as in the above-described embodiment.
It is not sent to U and no deadlock interrupt occurs.

〔Effect of the invention〕

As explained above, the present invention allows the initial setting value of the lock word access counter in the communication register to be freely set by an instruction, thereby preventing problems between tasks accessing shared resources or processor problems in case a deadlock occurs. This has the advantage that the optimal timing for the processor to issue a deadlock interrupt can be set.

Furthermore, by providing a mode in which deadlock detection is not performed in the present invention, while a processor that requires a long processing time is using shared resources in diagnostic mode, etc., a deadlock interrupt by a processor operating in normal mode is prevented. This has the effect of preventing unnecessary interruptions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed diagram showing the communication register 3 in FIG. 1, FIG. 3 is a block diagram showing the inside of each CPU, and FIG. 4 is a test and Detailed diagrams showing the contents of the set instruction, Figures 5(a) and 5(b) show the lock flag and lock word access counter times when a processor in normal mode and a processor in diagnostic mode lock shared resources, respectively. FIG. 1-1.1-2.1-3.1-4...CPU12...
- Communication register access control circuit, 3...Communicating register, 4-1.4-2...Selector, 5-1.5-2.
5-3.5-4...Register, 6...Subtractor, 7.
...Deadlock detection control circuit, 8...Decoder, 9
-1.9-2.9-3.9-4...Deadlock detection mask circuit, 10...Service processor, 11.
··shared memory.

Claims (1)

[Scope of Claims] 1. In an information processing system composed of a plurality of processors, one or more communication information storage means for storing control information and data related to communication between the processors; and the communication information storage means a command means for instructing reading, storing, and inspection of the communication information storage means; and access control for inspecting the contents of the communication information storage means in response to the command means and updating deadlock information in the communication information storage means based on the result. and deadlock detection means for inspecting the deadlock information, detecting the occurrence of deadlock, and reporting it to the processor, and deadlock detection means in lock control for resource acquisition when accessing shared resources in the system. An information processing system characterized by variable timing. 2. Claim 1 characterized in that it has one or more mode bits for enabling/disabling the deadlock detection means to report deadlock to the processor, and selectively reports detection of deadlock. The information processing system described.