JPS61213955A - Control system for bus occupation - Google Patents

Abstract

PURPOSE:To allows a module which time elapse after requesting is long to use a bus by sending bus use requests from respective modules to a priority determining circuit through a direct route, a flip-flop route, or a buffer route. CONSTITUTION:Bus use request signals REQ10-REQn from plural modules connected to the common bus are inputted to a priority circuit 4 directly through a multiplexer 8 when flip-flop routes 6 passed through flip-flops 6A and 6B are both free to obtain bus use permission signals GNT0-GNTn, but when one of the flip-flop routes is not free, they are sent to the other free route and enqueued temporarily. When either of the routes is free, they are sent to a buffer route 7 including a buffer 10 to wait for a flip-flop route 6 to become free, and sent to the route which becomes free through multiplexers 8A and 8B.

Description

[Detailed Description of the Invention] [Summary] In a data processing system in which a plurality of modules issue bus use request signals to request occupation of a common bus, a bus occupancy control circuit guides the bus use request signal to a priority circuit. The system is configured to prepare a direct route, a temporary flip-flop route, and a buffer route corresponding to the waiting room, and sends a permission signal as much as possible to requests that take a long time to pass. Disclosed is to cause the image to emanate.

[Industrial application field]

The present invention provides a bus occupancy control method, particularly a data processing system that requests exclusive use of a common bus and obtains the right to use it, by preparing a so-called waiting route and more accurately grasping and granting permission to those with long waiting times. Bus occupancy control system that issues signals [prior art] Conventionally, in this type of control, the bus is divided and used by each module in a time-sharing manner, and each period is assigned to each module. Fixed allocation is performed.

In this case, the maximum waiting time of each module can be easily calculated and the control mode can be simplified, but it is inefficient if the module does not use the allocated period. Furthermore, a fixed priority is given to the lotus usage between each module. However, in this case, there is a possibility that a module with a low priority will be kept waiting for a long time.

[Problem that the invention seeks to solve]

The present invention solves the above points. The purpose is to memorize changes in request signals from each module, and process the stored contents according to a determined priority order and according to the elapse of time from the time of the request.
The objective is to provide an efficient bus occupancy control method that averages out the waiting time of each module.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention, and the reference numeral 1 in the figure shows a block diagram of the principle of the present invention.
2-1 is a common bus, 2-1 is a module, 3 is a bus occupancy control circuit, 4 is a priority (PRY) circuit, 5 is a direct route, 6 is a flip-flop route, and 7 is a buffer route.

In the case of the present invention, each module 2 for a common bus 1
By storing changes in the request state from -i in the minimum change unit, and processing the stored contents in the order in which they were stored using each route 5.6.7 above, the oldest request, that is, This allows requests that have been waiting for a long time to be granted in order.

Each module 2-0.2-1.2 sharing common bus 1
-21. ,,, 'l -n to bus use request signal (R
EQO-n) are input to the bus occupancy control circuit 3 one by one, and from the bus occupancy control circuit 3, signals REQ0 to REQ0 to n
One bus permission signal (GNT0 to GNTn) corresponding to each module 2-0.2-1). It is output to , , . If there is a request signal from each module, it is guided to the priority circuit 4 according to the following algorithm.

That is, A) When the above-mentioned request signal REQi arrives when the flip-flop route 6 is in an empty state, the request signal REQi is immediately guided to the priority circuit 4 via the direct route 5, and the bus is not used. A grant signal GNT i can be received.

B) If the request signal REQi arrives when even one of the flip-flop routes 60 is not available, the flip-flop route 60 is guided to one of the available flip-flop routes and placed in a temporary standby state.

C) If the request signal REQi arrives when all of the flip-flop routes 6 are not free, the flip-flop is guided to the buffer route 7 and enters a waiting state in a waiting room, so to speak.

D) If there is a waiting request signal in the buffer route 7 when any one of the flip-flop routes 6 becomes vacant, the flip-flop route 6 whose time has elapsed longer is made to satisfy the root.

[Effect]

The bus occupancy control circuit 3 has routes 5, 6, and 7 as described above, and the priority circuit 4 processes the above request signals in the order of requests from route 5 and route 6, and uses the bus for the corresponding module. Issue a permission signal GNT I.

Correspondingly, the module 2-1 that has received the permission signal GNTi occupies the common bus 1 and sends and receives data, control information, and the like.

〔Example〕

FIG. 2 is a block diagram of one embodiment of the bus occupancy control circuit. Reference numerals 4.5.6.7 in the figure correspond to those in FIG.

As mentioned above, RE Q O-n is a direct route 5 which is input to the priority circuit 4 through the direct multiplexer (MPX) 8C, and a flip which is input through the flip-flop (FF) 9A or 9B through the MPX8A or MPX8B. - It is led to either the flop routes 6A, 6B or the buffer route 7 where it is input to the buffer 10 and waited. In the request generation detection circuit 1), RE
Changes in QO-n are monitored, and when any of REQ0 to n changes from “O” to “1”, a change signal (CHG) is sent.
Set to “1”.

The above FF9A and FF9B each have the number of bits corresponding to REQ0 to REQn, and each bit corresponds to the G
Reset by N T O-n.

Similarly, the buffer 10 has n data widths and m stages depth. *AZERO and *BZERO are signals that become 0'' when the contents of FF-A or Fl-B respectively reach θ''. The priority circuit 4 is the same as a general priority circuit, and for example, Q>l>2. , , >n are treated as having higher priority.

Figure 3 shows four modules (2-0, 2-1, 2-2,
2-3) represents a specific example.

■ REQO from 2-0.2-1.2-2 at the same time.

REQI and REQ2 are set.

At this time, CHG becomes “1” and *AZERO=*BZ
Since ERO=0, the REQ signal is input to the priority (PRY) circuit through MPX8C, and as a result, GNTO becomes "al".

REQ request was not accepted at the timing of ■■
I and REQ2 are set to FF9A, and the value of FF9A is input to the priority circuit 4, and then GNTl is sent out. Also, at this timing, the *AZERO signal becomes “
1”.

(2) Newly requested REQ3 is set to FF9B, and GNT2 is sent in response to REQ2.

■The REQO that was requested at the timing of ■ above is set in the buffer 10 because *AZERO-*BZERO="1", but at the timing of the above ■, F'
The content of F 9 A becomes "O". Also, at the same time, FF9
The contents of B are input to the priority circuit 4, and GNT3 is sent out.

■Since *AZERO=0 for FF9A, the contents set in buffer 10 at the timing of ■ above are sent to FF9A, and *BZERO=0 for FF9B, so priority circuit 4 has FF
The contents of 9A are input and GNTO is sent out. Also, at this timing, CHG-“0” and there is no new change in the request signal, so no setting occurs in the FF 9B or the buffer 10.

〔Effect of the invention〕

As described above, according to the present invention, it becomes possible to permit the use of the bus from those whose bus use requests have been kept waiting for a long time, so to speak, the bus use is averaged, and efficient control becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 shows the configuration of an embodiment of a bus occupancy control circuit which is a main part of the present invention, and FIG. 3 is a flowchart for explaining the operation. In the figure, 1 is a common bus, 2-1 is a module, 3 is a bus occupancy control circuit, 4 is a priority (PRY) circuit, 5 is a direct route, 6 is a flip-flop route, and 7 is a buffer route. There is. Patent applicant Fujitsu Ltd. Representative Patent Attorney Mori 1) Hiroshi (1 other person) Takumi Nto 5
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Claims (1)

[Claims] A plurality of modules (2-i
) and a bus occupancy control circuit (3) that manages requests from each of the modules (2-i) to occupy the common bus (1), the bus occupancy control circuit (3) is for each of the above modules (2
- determine the priority order for the bus use request signals (REQ0 to n) from
-i) is provided with a priority circuit (4) that issues permission signals (GNT0 to GNTn) only for the above-mentioned modules (2-i).
In order to guide REQ0 to n) to the above priority circuit (4),
Direct route (5) and flip-flop route (6)
and a buffer route (7), and the bus use request signals (REQ0-n) are sent to the direct route (5), then to the flip-flop route (6), and then to the buffer route (7) in the order above. The bus use request signals (REQ0-n) which are configured to be assigned to the lower route when the route is full and which are assigned to the buffer route (7) are assigned at least to the buffer route (7) in order of earliest assignment. A bus occupancy control system characterized in that when the flip-flop route (6) becomes vacant, data is transferred to the flip-flop route (6).