JP2002140293A - Arbitration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent occupation of a common bus by a bus access request having the same priority level. SOLUTION: This arbitration circuit is provided with a storage part 4 storing the latest permission state (the state of first and second bus access permission PM1 and PM2) to first and second bus access requests RQ1 and RQ2. In a control circuit 2, logical operation between the latest permission state inputted from the storage part 4 and first and second bus access requests RQ1' and RQ2' synchronized with clock signals CLK inputted from first and second D flip-flops 1a and 1b is carried out, and a bus access to the same bus access request is not allowed continuously until a bus access request having another priority level is allowed. In this way, occupation of a common bus by the bus access request having the same priority level can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration circuit for arbitrating access rights when devices such as a plurality of microcomputers access a shared bus.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional arbitration circuit. This arbitration circuit is synchronized with a first D flip-flop 1a to which a first bus access request RQ1 is input, a second D flip-flop 1b to which a second bus access request RQ2 is input, and a clock signal CLK. The first and second bus access requests RQ1 'and RQ2' output from the first and second D flip-flops 1a and 1b are input to one of the bus access requests according to a predetermined priority. RQ1 'and RQ2' are selected, and control signals CTRL0, CTRL1, and CTRL1 for permitting bus access to the selected bus access requests RQ1 'and RQ2'.
A control circuit 2 'for outputting CTRL2 and CTRL3, and a first JK in which the control signal CTRL0 is input to the J input terminal and the control signal CTRL1 is input to the K input terminal
A flip-flop 3a, and a second JK flip-flop 3b, to which a control signal CTRL2 is input to a J input terminal and a control signal CTRL3 is input to a K input terminal, from the output terminal of the first JK flip-flop 3a. The permission (first bus access permission) PM1 for the first bus access request is given, and the permission (second bus access permission) PM2 for the second bus access request is given from the output terminal of the second JK flip-flop 3b. Is to give. In addition, the priority can be changed for smooth bus access, or the next access right is given to a low priority bus access request when a plurality of bus access requests conflict. Some have been proposed.

[0003]

FIG. 4 is a timing chart of the above conventional example. For example, when the first bus access request RQ1 is made in a state where the first bus access permission PM1 is not issued (the state in which the first bus access permission PM1 is at the H level) (the first bus access request RQ1 is low). Level, a first bus access request RQ1 'synchronized with the clock signal CLK is input from the first D flip-flop 1a to the control circuit 2'. Control circuit 2 '
When only the first bus access request RQ1 'is input, the control signal CTRL0 at the H level is output for a time not longer than one cycle of the clock signal CLK. First JK to which two control signals CTRL0 and CTRL1 are input
When the control signal CTRL0 is input, the flip-flop 3a outputs an L-level first bus access permission PM1 to permit the bus access to the first bus access request RQ1.

Here, when the first bus access request RQ1 is continuously input and a subsequent request competes with the second bus access request RQ2, the control circuit 2 'sets a high priority in advance. First bus access request RQ
1 is given priority, and an H-level control signal CTRL0 is output to output an L-level first bus access permission PM1 to permit a bus access to the first bus access request RQ1.

That is, when bus access requests having the same priority (first bus access request RQ1 in the above example) are successively input, a bus access request with a lower priority (second bus in the above example) is issued. The bus access permission is not output for the access request RQ2). For this reason, there is a possibility that the chance of the bus access request having a low priority being granted a bus access with respect to the bus access request having a high priority may be significantly reduced, which may cause a malfunction of the entire system including the arbitration circuit. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an arbitration circuit capable of preventing bus access requests having the same priority from occupying a shared bus. It is in.

[0007]

According to a first aspect of the present invention, in order to achieve the above object, a plurality of bus access requests having predetermined priorities are inputted, and one bus access request is inputted in accordance with the priorities. An arbitration circuit for permitting a bus access by means of a storage means for storing the latest permission status for a plurality of bus access requests, selecting one bus access request from the plurality of bus accesses in accordance with a priority order, and permitting the bus access. Performs a logical operation on the latest permission status stored in the storage means and the bus access request, and continuously permits the same bus access request until a bus access request having another priority is permitted Control means for preventing a bus access having the same priority as the priority once granted. Scan without giving the bus permission in succession to the request, it cancels the prohibition of the bus permission after the bus permission is given to the bus access request with other priorities. This prevents bus access requests having the same priority from occupying the shared bus.

[0008]

FIG. 1 shows an embodiment of the present invention. However, since the basic configuration of this embodiment is the same as that of the conventional example, the same components are denoted by the same reference numerals and description thereof is omitted.

The arbitration circuit of this embodiment stores a latest permission status (the status of the first and second bus access permits PM1 and PM2) for the first and second bus access requests RQ1 and RQ2. It has. The storage unit 4 sequentially takes in the first and second bus access permissions PM1 and PM2 output from the first and second JK flip-flops 3a and 3b, stores the latest permission status, and stores the stored permission. The status is output to the control circuit 2.

On the other hand, in the control circuit 2, the latest permission status input from the storage unit 4 and the first and second synchronization signals synchronized with the clock signal CLK input from the first and second D flip-flops 1a and 1b. Bus access requests RQ1 ', R
A logical operation with Q2 'is performed so that the same bus access request is not successively permitted until a bus access request having another priority is permitted.

FIG. 2 is a timing chart for explaining the operation of the present embodiment. Here, the priority of the first bus access request RQ1 is changed to the second bus access request RQ1.
Assume that the priority is higher than the priority of 2.

As shown in FIG. 2A, a first bus access request RQ1 is made in a state where the first bus access permission PM1 is not issued (a state in which the first bus access permission PM1 is at H level). And (first bus access request RQ
1 becomes L level), as shown in FIG.
A first bus access request RQ1 ′ synchronized with the clock signal CLK is input from the D flip-flop 1a to the control circuit 2. When only the first bus access request RQ1 'is input, the control circuit 2 outputs the H-level control signal CTRL4 for a time not longer than one cycle of the clock signal CLK, as shown in FIG. In the first JK flip-flop 3a to which the two control signals CTRL4 and CTRL5 are input, when the control signal CTRL4 is input as shown in FIG. 2 (j), the first JK flip-flop 3a outputs an L-level first bus access permission PM1. The first bus access request RQ1
Allow bus access to In the storage unit 4, FIG.
As shown in (l), the first bus access permission PM1 is L
The outputs of the first and second JK flip-flops 3a and 3b are stored in synchronization with the first rise of the clock signal CLK after the change to the low level. (In this case, the first bus access permission PM1) is output to the control circuit 2 as the latest permission status.

Here, when the first bus access request RQ1 is made again as shown in FIG.
Performs a logical operation on the first bus access request RQ1 'and the permission status, and as a result, the permission status indicates the first bus access permission PM1, so that the clock signal CLK is output as shown in FIG. H for a time not longer than one cycle of
A level control signal CTRL5 is output. In the first JK flip-flop 3a, when the control signal CTRL5 is input as shown in FIG. 2 (j), the first bus access permission PM1 is inverted to the H level, and the first bus access request R1 is inverted.
Release the bus access permission for Q1.

Subsequently, when the second bus access request RQ2 is made in a state where the latest permission status stored in the storage unit 4 indicates the first bus access permission PM1, (the second bus access request RQ2). When RQ2 goes to L level), a second bus access request RQ2 ′ synchronized with the clock signal CLK is input from the second D flip-flop 1b to the control circuit 2 as shown in FIG. The control circuit 2 performs a logical operation on the second bus access request RQ2 'and the permission status, and as a result, the permission status indicates the first bus access permission PM1, so that as shown in FIG. The control signal CTRL6 at the H level is output for a time not longer than one cycle of the clock signal CLK. In the second JK flip-flop 3b to which the two control signals CTRL6 and CTRL7 are input, when the control signal CTRL6 is input as shown in FIG. 2 (k), the second JK flip-flop 3b outputs an L-level second bus access permission PM2. And the second bus access request R
The bus access to Q2 is permitted. In the storage unit 4,
As shown in FIG. 2 (l), the second bus access permission PM2
, The outputs of the first and second JK flip-flops 3a and 3b are stored in synchronization with the rising of the first clock signal CLK after the signal has changed to the L level, and valid bus access permission (second bus The access permission PM2) is output to the control circuit 2 as the latest permission status.

When the second bus access request RQ2 stops (when the second bus access request RQ2 becomes H level), the control circuit 2 makes one cycle of the clock signal CLK as shown in FIG. The control signal CTRL7 of the H level is output only for a time that is not longer than that. In the second JK flip-flop 3b, when the control signal CTRL7 is input as shown in FIG.
M2 is inverted to H level and the second bus access request RQ
2 is released from the bus access permission.

On the other hand, when the permission status is changed to the second bus access permission PM2 and the second bus access permission PM2 stops, the control circuit 2 sends the first bus access request RQ
As a result of performing a logical operation between 1 ′ and the permission status, the permission status has been changed to the second bus access permission PM2. Therefore, as shown in FIG.
The prohibition state of M1 is released and the control signal CTRL of H level is released.
4 is output. In the first JK flip-flop 3a,
As shown in FIG. 2 (j), when the control signal CTRL4 is input, an L-level first bus access permission PM1 is output to permit the bus access to the first bus access request RQ1. In the storage section 4, as shown in FIG. 2 (l), the first bus access permission PM1 changes to the first level in synchronization with the first rise of the clock signal CLK after the change to the L level.
And the outputs of the second JK flip-flops 3a and 3b are stored, and the valid bus access permission (first bus access permission PM1) is output to the control circuit 2 as the latest permission status.

As described above, in the present embodiment, the permitted bus access request is temporarily stored in the storage unit 4, and the permission status and the bus access request stored in the storage unit 4 are logically operated by the control circuit 2. Based on the result, the control circuit 2 does not continuously grant the bus access permission for the bus access request having the same priority as the priority once permitted,
Since the prohibition of the bus access permission is released after the bus access permission is given to the bus access request having another priority, the bus access request having the same priority is prevented from occupying the shared bus. As a result, the entire system including the device making the bus access request can be operated smoothly. In the present embodiment, the number of bus access requests is two. However, the present invention is not limited to this, and the same operation and effect can be obtained even with three or more bus access requests.

[0018]

According to the first aspect of the present invention, there is provided an arbitration circuit which receives a plurality of bus access requests having predetermined priorities and permits a bus access to one bus access request in accordance with the priorities. Storage means for storing the latest permission status for a bus access request; selecting one bus access request from a plurality of bus accesses in accordance with the priority order to permit the bus access; and storing the latest permission status and bus stored in the storage means Control means for performing a logical operation on the access request and not permitting a continuous bus access to the same bus access request until a bus access request having another priority is permitted. No bus access permission is given continuously for bus access requests having the same priority as the priority once granted. By releasing the prohibition of the bus access permission after the bus access permission is given to the bus access request having another priority, it is possible to prevent the bus access requests having the same priority from occupying the shared bus. This has the effect.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart for explaining the above operation.

FIG. 3 is a circuit block diagram showing a conventional example.

FIG. 4 is a time chart for explaining the above operation.

[Explanation of symbols]

 1a First D flip-flop 1b Second D flip-flop 2 Control circuit 3a First JK flip-flop 3b Second JK flip-flop 4 Storage unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hidehiko Nishikubo 1048 Kazumasa Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd. 72) Inventor Akira Yabuta 1048 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Works, Ltd. (reference) 5B061 BB07 BB16 BC02 GG13

Claims (1)

[Claims] 1. An arbitration circuit for receiving a plurality of bus access requests having predetermined priorities and permitting a bus access to one bus access request according to the priorities, the latest arbitration for the plurality of bus access requests. A storage unit for storing a status, and selecting one bus access request from a plurality of bus accesses according to the priority to permit the bus access, and performing a logical operation on the latest permission status stored in the storage unit and the bus access request An arbitration circuit comprising: control means for performing a bus access request for the same bus access request continuously until a bus access request having another priority is granted.