JP2848082B2 - DMA bus arbitration - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA arbitration system.
In particular, one direct memory access transfer (hereinafter
The present invention relates to a DMA arbitration system that arbitrates a circuit exclusively using a direct memory access bus (hereinafter, referred to as a DMA bus) for a long time in a DMA transfer.

[0002]

2. Description of the Related Art In a DMA transfer in which a memory is directly accessed without using a CPU to transfer data, it is necessary to arbitrate a DMA bus so that data can be transferred efficiently. In the conventional DMA bus arbitration method, arbitration is performed for a circuit that occupies a long-time DMA bus in one DMA transfer in the same manner as a circuit that occupies the DMA bus only for a short time in one DMA transfer. ing. That is, a circuit that occupies the DMA bus for a long time
Even when a DMA transfer request is issued to the A bus arbitration circuit, a DMA transfer request is issued from a circuit that occupies the DMA bus only for a short time in one DMA transfer, as in the case where a DMA transfer request is issued.
DMA transfer permission has been given from the DMA bus arbitration circuit. Further, the DMA transfer is divided in advance by a circuit that exclusively occupies the long-time DMA bus in one DMA transfer, and the DMA bus arbitration circuit does not occupy the long-time DMA bus in one DMA transfer.

[0003]

In this conventional DMA bus arbitration system, once a DMA transfer request source is given a DMA transfer permission, the DMA transfer request source withdraws the DMA transfer request to the arbitration circuit. Therefore, in the case of a DMA bus in which a DMA transfer request source competing for an extremely long DMA bus occupation time in one DMA transfer competes with another DMA transfer request source, the other DMA transfer request source becomes D.
There is a possibility that a long waiting time may be required until the MA transfer is permitted, and there is a problem that the DMA transfer cannot be performed at a high speed.

The present invention has been proposed in order to solve the problems of the prior art. In a DMA bus in which a plurality of circuits performing DMA transfer compete with each other, a long-time DMA bus is connected to one circuit. It is an object of the present invention to provide a DMA bus arbitration system that is not occupied.

[0005]

[MEANS FOR SOLVING THE PROBLEMS] To achieve this object
According to the present invention, a first circuit which occupies a DMA bus for a long time to perform a burst transfer in one DMA transfer and a plurality of second circuits which occupy a DMA bus only for a short time in one DMA transfer are provided. When the first circuit and the second circuit share the DMA bus and perform the DMA transfer, in the DMA bus arbitration method of performing arbitration for granting the DMA transfer permission to the first or second circuit that has requested the DMA transfer, the first circuit A register for storing the occupation time length that can occupy the DMA bus in one DMA transfer;
When there is an A transfer request, a counter for measuring the length of time during which DMA transfer is granted to the first circuit is compared with the exclusive time length from the above register and the time length measured by this counter. A comparing unit that outputs a coincidence signal when they match, and a first unit that outputs a coincidence signal from the comparing unit.
A DMA bus arbitration circuit is formed by a transfer wait signal sending unit that sends a transfer wait signal to the circuit of the first embodiment.
Inputting a transfer waiting signal from the DMA bus arbitrator circuit
And DMA bus request after performing the operation currently being executed
The signal is interrupted and the DMA bus needs to be restarted after a certain period of time.
By requesting a request signal, when one of the second circuits is in the process of requesting a DMA transfer, the first circuit does not occupy the DMA bus for a certain period of time in one DMA transfer. The control is performed so as to shorten the waiting time of the circuit.

[0006]

According to the above-described configuration, when a DMA transfer request is issued from another circuit to a circuit that performs a DMA transfer that occupies the DMA bus for a long time, the DMA bus is used for a predetermined time or more. Control without exclusive use becomes possible, and another circuit can perform DMA transfer after a short waiting time. After another circuit terminates the DMA transfer, the interrupted DMA transfer can be resumed. When there is no DMA transfer request from another circuit, the DMA transfer of the circuit that occupies the DMA bus for a long time can be continued without interruption.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific embodiment of the DMA bus arbitration system according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the DMA bus arbitration system. In this figure, a first circuit 1 and a plurality of second circuits 2 are D
The first and second circuits 1 and 2 are connected to the MA bus 3 and share the DMA bus 3. First circuit 1
Is a circuit that keeps occupying the DMA bus 3 for a long time in order to perform burst transfer in one DMA transfer, and a plurality of second circuits 2 from the 0th to the (n-1) th This circuit occupies the DMA bus 3 only for a short time in the DMA transfer.

[0008] These first and second circuits 1 and 2, D
The DMA bus arbitration circuit 4 arbitrates these circuits 1 and 2 in order to enable high-speed data transfer because they have a conflicting relationship in MA transfer. That is, D
The MA bus arbitration circuit 4 receives the DMA bus request signals LBRQ and BRQ0, BRQ from the first circuit 1 and the second circuit 2.
RQ1,..., BRQ (n-1) are respectively received, arbitrated, and a transfer permission signal L is sent to one of the circuits.
One of BAK, BAK0, BAK1,..., BAK (n-1) is returned.

In a register 5, which is a storage unit in the DMA bus arbitration circuit 4, a time length S in which the first circuit 1 can occupy the DMA bus 3 in one DMA transfer is digitized and stored in advance. I have. Further, the DMA bus arbitration circuit 4 receives the DMA bus request signals B transmitted from the plurality of second circuits 2.
.., BRQ (n−1), and the logical product of the logical sum output and the transfer permission signal LBAK sent to the first circuit 1 is calculated. The timing of the counter 6 in the arbitration circuit 4 is started. That is, in the counter 6 forming a timekeeping unit, when any one of the plurality of second circuits 2 is requesting a DMA bus transfer, the transfer permission signal LBA is transmitted to the first circuit 1.
The length of time for returning K is measured. This time length is the second time since the first circuit 1 is performing the DMA transfer.
Corresponds to the length of the waiting time until the transfer permission signal is returned to the circuit 2.

[0010] The outputs of the counter 6 of the register 5,
It is sent to the comparator 7 in the DMA bus arbitration circuit 4 and when the two outputs match, that is, the time length S during which the first circuit 1 can occupy the DMA bus 3 and the transfer permission signal LB to the first circuit 1
When the time length in which AK is continuously returned matches, "1" corresponding to the match signal is output from comparator 7. DM
The transfer wait signal sending section 8 in the A bus arbitration circuit 4 sends the transfer wait signal WAIT to the first circuit 1 in synchronization with the input of "1" from the comparator. Here, the comparator 7 and the transfer waiting signal transmitting section 8 constitute a transfer waiting signal generating section.

[0011] The first circuit 1 having a DMA transfer interruption means
Is, when this transfer waiting signal WAIT is sent,
After performing the read or write operation to the currently executing memory, the transmission of the DMA bus request signal LBRQ to the DMA bus arbitration circuit 4 is interrupted. With this, DMA
The transmission of the transfer permission signal LBAK returned from the bus arbitration circuit 4 to the first circuit 1 is stopped, and the transfer permission signal is returned to one of the second circuits 2 which has been requesting the DMA bus. . As a result, the DMA transfer operation of the second circuit 2 in the waiting state is started.

[0012] The first circuit 1, DMA bus request signal LB
After interrupting the transmission of the RQ, the DM
An A bus request signal LBRQ is sent to the DMA bus arbitration circuit 4. In response to this, the DMA bus arbitration circuit 4 returns the transfer permission signal LBAK to the first circuit 1, so that the first circuit 1 can resume the DMA transfer from the address following the temporarily interrupted memory address.

[0013] Next, the operation of the DMA bus arbitration scheme having such a configuration with reference to the waveform diagram of FIG.
The signals shown in the waveform diagrams are all positive logic. While the transfer permission signal LBAK is not returned from the DMA bus arbitration circuit 4 to the first circuit 1, the transfer permission signal is sequentially returned to the requested second circuit 2. In the example of FIG. 2, the DMA bus request signal BRQ0 is followed by the DMA bus request signal BRQ1
Therefore, the transfer permission signal BAK1 is returned following the transfer permission signal BAK0.

The DMA bus request signal LB from the first circuit 1
After the RQ is transmitted, the (n-1) th and 0th second
DMA bus request signal BRQ (n-1)
And BRQ0 are transmitted, the DMA bus arbitration circuit 4
After the transfer permission signal LBAK is returned to the first circuit 1 from the controller 5, when a time length S predetermined by the register 5 has elapsed, the transfer wait signal WAIT is sent to the first circuit 1. In response to this, the first circuit 1 outputs the DMA
Since the bus request signal LBRQ is dropped, the DMA bus arbitration circuit 4 stops returning the transfer permission signal LBAK to the first circuit 1, and transmits the transfer permission signal BAK to the (n-1) -th second circuit 2. (N-1) is returned. Thereafter, the transfer permission signal BAK0 is returned to the 0th second circuit 2. When the first circuit 1 drops the DMA bus request signal LBRQ and the DMA bus request signal LBRQ
Since the transfer is resent to the bus arbitration circuit 4, the DMA bus arbitration circuit 4 returns the transfer permission signal LBAK to the first circuit 1 after returning the transfer permission signal BAK0, and performs the DMA transfer operation by the first circuit 1. Is resumed.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist.

[0016]

As described above, according to the present invention, D
The MA bus arbitration circuit can be used for a long time in one DMA transfer.
For circuits that exclusively use the MA bus, DMA
When there is a transfer request, a transfer waiting signal can be transmitted. As a result, the circuit that occupies the DMA bus for a long time is:
Since the DMA transfer is temporarily interrupted after the transfer waiting signal is recognized, a circuit that requests DMA transfer other than this circuit can obtain the DMA transfer permission without waiting for a predetermined time or more. Also, when there is a DMA transfer request only from a circuit exclusively using the DMA bus for a long time, the DMA transfer can be continued without interruption. Therefore, when a plurality of circuits share the DMA bus and perform the DMA transfer, there is no problem that a long wait occurs, and the DMA transfer is performed at a high speed.
There is an advantage that transfer can be performed.

[0017] Especially for circuits that occupy a long time DMA bus.
A function to suspend DMA transfer has been added.
Other circuits while giving priority to the circuit exclusively using the DMA bus between
Can be prevented from having a long waiting time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a DMA bus arbitration system according to the present invention.

FIG. 2 is an operation waveform diagram for explaining the operation of the DMA bus arbitration method.

[Explanation of symbols]

1 A first circuit that occupies a DMA bus for a long time 2 A plurality of second circuits that occupy a DMA bus only for a short time 3 DMA bus 4 DMA bus arbitration circuit 5 Register 6 Counter 7 Comparator 8 Transfer waiting signal transmission unit

Claims (1)

(57) [Claims] A first circuit that occupies a DMA bus for a long time in one DMA transfer and a plurality of second circuits that occupy a DMA bus only for a short time in one DMA transfer are DM
When performing DMA transfer by sharing the A bus, DM
In a DMA bus arbitration system for performing arbitration for granting a DMA transfer permission to the first or second circuit that has issued the A transfer request, the occupation time length in which the first circuit can occupy the DMA bus in one DMA transfer in advance A counter that measures the length of time during which DMA transfer is granted to the first circuit when there is a DMA transfer request from any of the second circuits; A comparison unit that compares the length with the length of time measured by this counter and outputs a match signal when the two match, and a transfer wait signal is sent to the first circuit when a match signal is input from the comparison unit. DMA bus arbitration circuit by the transfer waiting signal generating portion for sending is, after the first circuit, inputs the transfer waiting signal from the DMA bus arbitrator circuit Then, of performing the operation currently being executed
The DMA bus request signal is interrupted and
By requesting the DMA bus request signal again , when any one of the second circuits is in the process of requesting the DMA transfer, the first circuit does not occupy the DMA bus for a certain period of time in one DMA transfer. And a DMA bus arbitration method characterized by shortening the waiting time of the second circuit.