JPS62197851A - Bus controller - Google Patents

Abstract

PURPOSE:To ensure the flexibility and expansion property and to attain the effective bus control by forming a bus arbiter in the form of such an intelligent system as a 1-chip microcomputer, etc., and controlling the action of the arbiter by a program. CONSTITUTION:A bus arbiter ABT consists of a processor CPU, a random access memory RAM, a read only memory ROM, a timer circuit TIM, an external interface circuit IOC, and a bus control circuit BC. The control circuit BC serves as an interface which connects the processor CPU forming the bus arbiter and a common bus CB and also controls plural requesters which are connected to the CPU by the bus CB according to the instruction of the CPU. Here the transfer of the control signal is prescribed by the control procedure of a VME bus system between the circuit BC and plural requesters although this prescription is not so strict.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bus arbiter (bus control device), and relates to a technique that is effective when applied to a bus arbiter of a computer system having a plurality of bus masters, for example. .

[Conventional technology]

For example, in August 1982, a method for concentrating the lotus acquisition control function in a single bus arbiter (bus control device) in a computer system having multiple bus masters was proposed.
PMI Manufacturers Group (V) in the United States
M E-Manufactures -Group
) published rVME bus specification manual (VME bu
s5specification Manual)
(Rev, B) J's CIIAPTER3,3
It is described on pages -1 to 3-22. The bus arbiter, including this VME bus method, employs a bus control method that is fixed in hardware according to a predetermined bus control procedure.

[Problem that the invention seeks to solve]

The present inventors have discovered that such a conventional bus arbiter has the following problems. In other words, as mentioned above, since the bus arbiter uses a fixed bus control method based on a predetermined bus control procedure, (1) the priority order for each requester is fixed, and the number of requesters is If the number increases, the waiting time for requesters with lower priority becomes longer.

(2) Since the bus arbiter is fixed in terms of hardware, it is not affected by changes in the bus control method or computer system.
Lack of scalability and flexibility.

(3) Since the bus arbiter does not know the bus usage status, it is not possible to efficiently manage the bus according to the usage status.

(4) Since the bus arbiter does not know the status of the bus usage time or waiting time, it cannot detect system deadlocks due to failures, etc., or long waiting times of low-priority requesters.

These are issues such as.

An object of the present invention is to provide a bus arbiter (bus control device) that has flexibility and expandability and performs efficient bus control.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
The bus arbiter is configured as an intelligent system, such as a one-chip microcomputer, having a processor, a storage device, a timer circuit, an external interface, a bus control circuit, etc., and its operation is controlled by a program.

[For production]

According to the above-mentioned means, the bus controller can have flexibility and expandability in its control method, priority order, etc., and efficient bus management can be performed using a timer function and the like.

〔Example〕

FIG. 1 shows a bus arbiter ABT to which this invention is applied.
A block diagram of one embodiment is shown.

The hash arbiter AB T of the embodiment includes a processor CPU, a random access memory RAM, a read-only memory ROM, and a timer circuit T I as shown in the figure.
M, an external interface circuit 10C, and a bus control circuit BC.

The bus control circuit BC constitutes an interface for connecting the processor CPU constituting the bus arbiter and the common bus CB, and controls a plurality of requesters connected to it via the common bus CB according to instructions from the processor cPU. Although not particularly limited, the procedure for transmitting and receiving control signals between the bus control circuit BC and the plurality of requesters is defined, for example, by the control procedure of the VME bus method described above.

The processor CPU controls and manages bus arbiter operations according to a program stored in a read-only memory ROM. The symbol RAM is a random
This is an access memory and is used for temporary storage of data etc. during calculations by the processor CPU, and as a stack area when an interrupt occurs. The operation of the timer circuit TIM is controlled by the processor CPU, and is used for time management to keep track of the usage time of the common bus CB and the waiting time of each requester. External interface I
The operation of the OC is controlled by the processor CPU, and the OC serves as an input/output interface for changing priorities and the like instructed from outside the illustrated bus arbiter, that is, the bus control device.

Although not particularly limited, the above read-only memory R
OM, random access memory RAM, timer circuit 'T'1M, and external interface IOC:
It is connected to the processor CPU via an input/output bus, and processing by each is performed at a normal interrupt level that can be masked. On the other hand, bus control circuit BC
Processing is performed at a so-called non-maskable interconnected level where interrupts cannot be masked because bus control processing is performed immediately.

FIG. 2 shows a connection diagram for explaining the connection state and control system between the bus arbiter and each requester. As shown in the figure, the bus arbiter ABT has multiple requesters SBC1 to SBC5B via the common bus CB.
Cn is connected.

Although not particularly limited, these multiple requesters 5BC
The I-SBCn are divided into groups according to their priority ranks and connected to the common bus CB. The priority of each group is managed by the processor CPU shown in FIG. 1 of the bus arbiter ABT. Further, for a plurality of requesters at the same level, priorities are determined by a daisy chain configuration.

As described above, the control procedure between the bus arbiter ABT and each requester is performed based on the VME bus method.

The common bus CB consists of the following signal lines shown in FIG. 2, in addition to several signal lines with special functions (not shown):

Bus request signals BRO to BR4 are sent to the bus arbiter ABT when each requester wants to use the common bus CB.
In order to make a bus use request, the requester asserts the signal from a high level to a low level, for example. The priority of the bus request signal applied to each bus request signal line is determined by the processor CPU of the bus arbiter ABT. Therefore, which bus request signal line each requester should be coupled to is determined by its respective priority.

The bus ground output signal BGOOUT-BG40UT is
When granting permission to occupy the common bus CB as a bus mask to a requester that has made a bus use request via the bus request signal line, one of the bus request signals that corresponds to the bus request signal for which the bus use request was made goes high. Asserted from level to low level. This bus ground 1 output signal BGOOUT-BG40UT is used as the bus ground input signal BGOIN-BG4 IN when there are multiple requesters whose priorities are set to the same level.
Together, they form a daisy chain.

That is, when multiple requesters with the same priority are connected to the bus request signal BRO, for example, the pass ground output signal BGOOUT is transmitted by the requestor closest to the bus arbiter ABT in the daisy chain.
First, it is taken in as the pass ground input signal BCOINI. When this requester issues a bus use request, it accepts the pass ground input signal BGOTNI as it is, negates the bus request signal to high level, and sets the bus busy signal BBSY to the roaming level. If no request to use the bus has been issued, the pass ground output signal BGOOUTI is set to low level and sent to the next requester. The requester with the second priority takes in Gogo as the pass-ground input signal BCOIN2 at this pass-ground output signal τ. When this requester is outputting a bus request signal, it receives the pass ground input signal BCOIN2 as it is, negates the bus request signal to high level, and sets the bus busy signal BBSY to low level. Thereafter, similar operations are repeated to form a disease chain 7 made up of a plurality of requesters at the same level.

As mentioned above, the bus busy signal BBSY is asserted from a high level to a low level by a requester whose bus use request has been accepted by the bus arbiter ABT, and is a level indicating that the common bus CB is occupied. It is something that is done.

When the common bus CB is occupied by one bus master, the bus clear signal BCLR clears the common bus CB for the bus mask with a lower priority when a bus use request is generated from another requester with a higher priority. This is a signal line for instructing to open.

As described above, the above bus control process is managed by the processor CPU of the bus arbiter ABT. That is, the plurality of requesters connected to each bus request signal line are ranked according to priorities displayed in, for example, a random access memory RAM or a read only memory ROM. Furthermore, the processor CPU can grasp the usage status of the common bus CB by measuring how long the common bus CB is being used by which rank of the bus mask using the timer circuit TIM. Further, the processor CPU similarly uses the timer circuit TMM to ascertain how long a bus use request from a requester with a low priority is waiting due to the common bus operation management of a bus master with a high priority. be able to. The processor CPU determines the priority of the requester and the processor CPU depending on the usage status of these common buses CB and the waiting time of the requester.
Change own operating mode. This makes it possible to efficiently manage the common bus CB and to preferentially accept requesters who have been waiting for a long time.

The bus control method of the processor CPU can be arbitrarily changed by replacing the program in the read-only memory ROM that determines it. In addition, the priority of each requester group displayed in the random access memory RAM or read-only memory ROM can be determined via the external interface IOC.
It can be rewritten using an external computer or keyboard and can be changed to any priority order.

As shown in the above embodiment, when the present invention is applied to a bus arbiter of a computer system having a plurality of bus masks, the following effects can be obtained. That is, (1) The bus arbiter can be controlled by making the bus arbiter an intelligent system, such as a one-chip microcomputer, which has a processor, a storage device, a timer circuit, an external interface, a bus control circuit, etc., and controlling this by a program. The effect is that methods, priorities, etc. can be made flexible and expandable.

(2) Item (1) above has the effect that it is possible to easily respond to changes in the bus control method, changes in the configuration of requester groups, etc. by, for example, replacing the program in the read-only memory ROM. It will be done.

(3) Through time management using a timer circuit, the processor of the bus arbiter can grasp the occupied time of the common bus by each requester, the waiting time of bus use requests, the number of times of use, etc., and improve efficiency according to the usage status of the common bus. In addition to being able to perform common bus operation management,
An effect can be obtained in that the priority order can be changed midway to allow a requester who has been waiting for a long time to preferentially use the common bus.

(4) By using various microprocessors that are already in practical use, one-chip microcomputers, etc., it is possible to easily realize a bus arbiter that is compatible with the present invention.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, although the bus control system of this embodiment employs the VME bus system as its bus control system, it is not limited to this, and various bus control systems may be used. Furthermore, the bus arbiter shown in FIG. 1 is not a one-chip one, but may be configured with a plurality of chips on a plurality of boards. Furthermore, various embodiments can be adopted, such as the block configuration of the bus arbiter and the configuration of the signal line of the common bus.

In the above explanation, the invention made by the present inventor has mainly been explained in the case where it is applied to a bus arbiter of a one-chip microcomputer system having a plurality of bus masters, which is the field of application in which the invention was made, but the present invention is not limited thereto. Instead, it can be used, for example, as a bus arbiter in a computer system consisting of a plurality of computers connected by one common bus. The present invention is applicable to bus control of an I10 bus having at least a plurality of bus masters.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, the bus arbiter is an intelligent system such as a one-chip microcomputer that has a processor, a storage device, a timer circuit, an external interface, a bus control circuit, etc., and is controlled by a program to control the bus arbiter's control method and priorities. It is possible to provide flexibility and expandability in the ranking determination method, and to perform efficient bus management according to the usage status of the common bus.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the bus 7'-biter (bus control device) to which the present invention is applied, and FIG. 2 shows a connection method between the bus arbiter of FIG. FIG. 3 is a connection diagram for explaining a control method. CPU...processor, BC...bus control circuit, R
AM...Random access memory ROM...Read only memory, TIM...Timer circuit,
CB...Common bus, IOC...External interface ABT...Bus arbiter, 5BCO to 5BCn...
requester

Claims (1)

[Claims] 1. A bus control circuit for monitoring bus usage according to a predetermined program and transmitting and receiving a plurality of signals necessary for bus control to and from a plurality of requesters via a common bus. bus control device. 2. The bus control device includes a processor, a storage device that stores programs and data for controlling the processor, and a timer circuit that is controlled by the processor and counts the common bus occupation time and requester waiting time. , an external interface for the processor to transmit and receive data with an external device, and a bus control circuit that is controlled by the processor and that transmits and receives a plurality of signals necessary for bus control to and from a plurality of requesters via a common bus. The bus control device according to claim 1, characterized in that the bus control device includes: 3. The processor manages the priorities of a plurality of requesters or a group of requesters connected to the common bus, and adjusts the priorities according to the common bus occupation time obtained by the timer circuit and the waiting time of the requesters. 3. The bus control device according to claim 1, wherein the bus control device is capable of changing the bus control device and the operation mode. 4. The first aspect of the present invention is characterized in that the processor is capable of changing the priority order of the requester or a group of requesters and the operating mode of the processor itself in accordance with instruction information input via the external interface. 3. The bus control device according to item 1, 2 or 3.