JPS63200259A - Control system for application of bus - Google Patents

Abstract

PURPOSE:To ensure the rational control for distribution of the bus application rights by transferring successively these bus application rights in accordance with the priorities decided by a delay chain. CONSTITUTION:Plural microprocessors MPU0-MPUn that can be served as bus masters are connected in parallel in a daisy chain system. The bus request signals produced from these bus masters are monitored with each other and other bus request signals are produced as long as said monitored bus request signals are kept under the inactive states. In addition, to this signal producing function, a function is provided to transmit immediately an activated bus permission signal of the daisy chain input to the daisy chain output as long as the bus masters produce no bus permission signal of their own, and a function which disuses the bus application right when a bus master ends its own bus application right and the bus request signals of other bus masters are active.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus usage control system, and relates to a technique that is effective when applied to, for example, a daisy chain system.

[Conventional technology]

A daisy chain method is used to control bus occupancy when a single bus is shared by multiple devices. Although the response speed of this daisy chain method slows down in proportion to the number of devices, it is simple in configuration and easy to expand. Regarding such a daisy chain system, there is, for example, Microcomputer Handbook J, page 303, published by Ohmsha on December 25, 1985.

[Problem that the invention seeks to solve]

In the above daisy-chain method, the device (bus requester) that is located closest to the arbiter that manages bus occupancy first receives the bus permission signal, and if it is requesting bus use, it receives the bus permission. The bus is acquired and the bus permission signal is sent to other devices as inactive. If the device is not requesting the bus, it activates and transmits the bus use permission signal to the next device.

In the above daisy chain method, when there are many devices with the same priority level and each device makes frequent requests to use the bus, the device at a lower position simply continues to issue bus request signals and uses the bus. I can't get any rights.

An object of the present invention is to provide a new bus usage control method that realizes rational allocation management of bus usage rights.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a system in which multiple devices that can act as bus masters are connected in parallel in a daisy chain manner, each bus master monitors the bus request signal issued from the other bus masters, and determines whether the bus request signal is in an inactive state. A function to issue a bus request signal on the condition that the bus is not issued, and a function to immediately send the activated bus grant signal of the daisy chain input to the daisy chain output when the bus does not issue a bus request signal. A function is added for relinquishing the right to use the bus when the bus request signal of another bus master is in an active state when the bus has been used.

[For production]

According to the above means, when multiple bus use request signals are issued at the same time, the bus use right is not monopolized by the bus master with a higher priority, and the bus use right is sequentially granted according to the priority by the daisy chain. Receipt can be made to carry out delivery.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of an information processing system to which the present invention is applied.

In the information processing system of this embodiment, N+1 microprocessors such as microprocessors MPU0 to MPUn (or a device that can serve as a bus master such as a direct memory access control device) are connected to an address bus AB and data It is coupled to bus DB in parallel.

A plurality of such devices connect the bus AB.

The right to use the bus for sharing by the DBs is controlled by the arbiter ABT and the logic circuit LOG that constitutes a bus requester provided in each of the devices MPUO to MPUn.

The above arbiter ABT and the logic circuit LOG as a path requester of each microprocessor (path requester > MPU0 to MPUn) are coupled by a daisy chain method. Certain request lines and approval lines are shown.

Each path requester LOG above has the following four machines m(1)
~(4).

Function (1) is to monitor bus request signals issued by other bus masters. This monitor function is
The following functional conditions are considered.

Function (2) is supplied from a microprocessor or the like as a path requester on the condition that the bus request signal BR from another device output through the request line by function (1) is inactive. A bus request signal BR is sent to the request line.

Function (3) causes the activated bus grant signal of the daisy chain input, which is supplied through the grant line, to be immediately sent to the daisy chain output when the path requestor, such as a microprocessor, is not issuing a bus request signal. Furthermore, if a bus request is being made, the right to use the bus is acquired and an inactive bus permission signal is output to the daisy chain output.

When the bus has finished using the bus, the bus relinquishes the right to use the bus when the bus request signal of another bus master is active according to (1) above.

In the above configuration, for example, when all the microprocessors MPU0 to MPUn as path requestors simultaneously issue a bus request signal, functions (1) and (2) cause the bus requester LOG in all the microprocessors MPU0 to MPUn to activates the bus request signal BR.

Arbiter ABT sends out a bus use permission signal BG from the approval line. As a result, the permission signal BG is unconditionally supplied to the microprocessor MPU0 connected closest to the arbiter ABT, so that the microprocessor MPU0 acquires the right to use the bus. At this time, the path requester LOG of the microprocessor MPU0 sends an inactive permission signal BG to its daisy chain output.

This allows the microprocessor MPUI or MP
Un acquires the right to use the bus. When this microprocessor MPU0 finishes using the bus, the right to use the bus is immediately relinquished by the above function (4). As a result, the bus use permission signal BG output from the arbiter ABT is
is the path requestor LOG of the microprocessor MPU
In this case, the function (2) prohibits the issuance of the bus request signal BR again, and the function (3) activates and outputs the bus use permission signal BG. will be granted the right to use the bus. Thereafter, in the same way, the microprocessor MPUn designated as the lowest priority is also N+
You can obtain the right to use the bus for the first time.

Note that, for example, two microprocessors MPU0 and MP
If the UI issues the bus request signal BR at the same time, the other microprocessors MP03 to MPUI will wait until the two microprocessors MPU0 and MPUI finish using the bus.
Issuance of bus request signal BR from MPUn is performed by the above function (
2) is prohibited. The above microprocessor M
When the use of the bus by PU0 and MPUI is finished, the bus request signals from the microprocessors MPU3 to MPUn, etc., which have been kept waiting, are simultaneously issued from their respective path requesters LOG. This eliminates the problem of a microprocessor with a higher priority constantly changing hands and acquiring the right to use the bus.

Note that the arbiter ABT issues the bus use permission signal with multiple levels of priority. Therefore, when bus permission signals are issued simultaneously from bus masters assigned to multiple levels, the above-mentioned bus usage rights are handed over in order of priority.

The effects obtained from the above examples are as follows. That is, (1) In a system in which multiple devices that can become bus masters are connected in parallel in a daisy chain manner, the bus request signals issued to each bus master from other bus masters are monitored, and the bus request signal is determined. A function to issue a bus request signal on the condition that it is in an inactive state, a function to immediately send an activated bus grant signal of the daisy chain input to the daisy chain output when the bus request signal is not issued by itself, and A function is added to relinquish the right to use the bus when the bus request signal of another bus master is active when the bus master itself has finished using the bus. As a result, when multiple bus use request signals are issued at the same time, the right to use the bus is not monopolized by the bus master with a higher priority, and the right to use the bus is received and handed over sequentially according to the priority using the daisy chain. The effect is that it can be done as desired.

(2) By incorporating a relatively simple circuit that realizes the above functions into a device that can serve as a bus master, such as a microprocessor, and by connecting each device using a daisy chain method, a simple system configuration can be achieved. This provides the advantage of being able to manage the lines used by the bus.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the path requester may be constituted by an independent semiconductor integrated circuit. Furthermore, the specific circuit may be of any type as long as it realizes the above-mentioned functions. Further, the arbiter ABT may have multiple levels of priority, and may connect devices using a daisy chain method depending on each bell.

The present invention can be widely used in bus usage control systems using a daisy chain system.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, in a system in which multiple devices that can act as bus masters are connected in parallel in a daisy chain manner, each bus master monitors the bus request signal issued from the other bus masters, and determines whether the bus request signal is in an inactive state. A function to issue a bus request signal on the condition that the bus is not issued, and a function to immediately send the activated bus grant signal of the daisy chain input to the daisy chain output when the bus does not issue a bus request signal. A function is added to relinquish the right to use the bus when the bus request signal of another bus master is in an active state when the bus has been used. As a result, when multiple bus use request signals are issued at the same time, the right to use the bus is not monopolized by the bus master with a higher priority, and the right to use the bus is received and handed over sequentially according to the priority using the daisy chain. You can do as you like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. MPU0 to MPUn... Microprocessor (bus master), LOG... Bus requester (logic circuit) ABT
...Arbiter, AB...address bus, DB...data path

Claims (1)

[Claims] 1. A function of monitoring a bus request signal issued by another bus master and issuing a bus request signal on the condition that the bus request signal is inactive; A function that immediately sends the activated bus permission signal of the daisy chain input to the daisy chain output when no signal is issued, and a function that allows the bus to be used when another bus master's bus request signal is active when the bus master itself has finished using the bus. A bus usage control system characterized in that a plurality of bus masters having a function of relinquishing rights are connected in parallel in a daisy chain manner. 2. The bus usage control system according to claim 1, wherein each of the above functions is built into a semiconductor integrated circuit device constituting an information processing device that can serve as a bus master.