JPH0218657A - Multiple bus microcomputer system - Google Patents

Abstract

PURPOSE: To make a processor able to preferentially use a system bus conditionally by providing plural conductors dedicated to the arbitration of access to the system buses of plural function units and transmitting preferential use signals. CONSTITUTION: When an arbitration monitoring mechanism 335 recognizes that one or plural devices request common resources, a contention device generates signals corresponding to respective priority order levels and drives plural arbitration conductors 340 dedicated to the function. Connection between the plural devices and the arbitration conductors 340 is adjusted so as to make the conductor take the priority order value of the circuit of a highest priority order for driving the arbitration conductor. Thus, when the respective devices compare the priority order value on the arbitration conductor 340 with their own priority order values, whether or not the device of a higher priority order for competing the access to the bus is present is recognized. Thus, a CPU 225 accesses system bus resources distributed by the arbitration mechanism 335 in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION A. INDUSTRIAL APPLICATION The present invention relates to an 82385 operating in master mode.
In the 388/82385 microcomputer, 8
0386 to realize the start of bus arbitration.

B. Background information regarding the prior art 80386, its characteristics, and its use in microcomputer systems, including cache memory subsystems, can be found in Intel's r803
8 (3 Introduction).

the 80386) J (April 198t3),
and “80386 Hardware Manual (803861(
Reference Manual)
J (1,986). 82385
The characteristics and operating performance of Intel's R82385 high-performance 32-bit cache controller (8238511i)
gh Performance 32-BitCach
e Controller) J (19,8' 7
year).

Apparatus for distributing resources among a plurality of potential users are disclosed in Japanese Patent Application No. 82-327583 and Japanese Patent Application No. 33-221.
No. 77 and U.S. Patent Application Serial No. 1.02 E390, filed September 30, 1987. Those applications are based on single-bus microcomputer
Computer bus communication between multiple devices in a system
It describes the distribution of resources such as access to subsystems and memory. This distribution of resources is generally called arbitration. The arbitration apparatus described in the above application uses distributed arbitration with a central supervisory mechanism to allocate a common resource to one of a plurality of potential users. However, since the supervisor or monitoring mechanism is controlled by the CPU,
If a PU requires access, the CPU can control the monitoring mechanism so that it can receive and receive access to the common resource as needed.

A microcomputer that includes a cache subsystem is architecturally quite different from a microcomputer system that does not have a cache subsystem. A microprocessor system that includes a cache subsystem operates as a dual bus device. Specifically, in a microcomputer system including a cache subsystem, a first bus (
CPtJ local bus). Other devices are connected to another bus (system bus).

These other devices include main storage, input/output devices, and auxiliary devices. In addition to the aforementioned devices, a cache controller is also connected to the system bus.

The cache subsystem generally relieves the system bus of most memory accesses that would otherwise have to be incurred. That is, as long as the CPU can obtain information from cache memory, the CPU does not require access to the system bus in any particular cycle. Therefore, at the same time, other devices can use the system bus for other operations. This is expected to result in fewer system bus cycles actually used by the CPU. usually,
The cache controller is connected to both the system bus and the CPU local bus.

One of the functions of the cache controller is to oversee the arbitration supervisory mechanism, which in single bus systems would be overseen by the CPU.

823, which is one cache controller currently available.
85 has a function of operating in a slave manner. 8238
When operating in five-master mode and monitoring the arbitration supervisory mechanism, there is no longer a mechanism for the CPU to contend for system bus resources.

C1 Problems to be Solved by the Invention Therefore, an object of the present invention is to provide a multi-bus microcomputer system having a cache control unit that monitors an arbitration monitoring mechanism, in which a CPU uses system bus resources distributed by the arbitration mechanism. The goal is to provide a mechanism that allows access.

Means for Solving the D1 Problem The arbitration monitoring mechanism described in said application is responsive to arbitration request signals commonly provided by a plurality of devices. When the arbitration supervisor recognizes that one or more devices have requested a common resource, it signals the beginning of arbitration by changing the state of the conductor (ARP/GRANT has access to all competing devices). When competing devices learn of a change in state on this conductor that signals the beginning of an arbitration period, they generate signals corresponding to their respective priority levels, and these signals cause multiple arbitrations dedicated to this function. Drive the conductor.

The connections between the plurality of devices and the arbitration conductor are arranged such that the conductor assumes the priority value of the highest priority circuit driving the arbitration conductor. Therefore, each device, by comparing the priority value on the arbitration conductor with its own priority value,
It can recognize if there are higher priority devices competing for access to the bus. At the end of a given arbitration period, the ARB/GRANT conductor changes state. This begins a grant period during which a competing device with a priority value equal to the priority value on the arbitration conductor gains control of the common resource and begins a bus cycle.

Additionally, as described in that application, there is another conductor dedicated to a preemption or PREEMPT signal, which is generated to terminate access to a device that has received access to system resources. That is, devices that receive access to system resources and are using those resources receive preemption.
), it is necessary to terminate the use of system resources. When the device granted priority use in this manner has finished using the common resource, the arbitration supervisor begins a new arbitration cycle as described above.

In microcomputer systems that include a cache subsystem, the CI that accesses the cache (and therefore does not require access to the system bus)
``A U-cycle is a cycle of minimum duration or a cycle of wait or zero states.

When CPU cycles exceed this minimum, it signals that the system bus is needed by the CPU. That is, a CPU cycle longer than the minimum time signals the CPU's need for a common resource, the system bus.

According to the invention, the CPU is provided with means for generating a PREEMPT signal which causes a device that has gained access to the bus to terminate its access by means of an arbitration mechanism, as already explained.

As explained below, the generation of the PREEMPT signal by the CPU is controlled by detecting CPU cycles of longer duration than the cycles needed for a cache address.

However, the CPU's use of system resources is adjusted to last as long as possible. Specifically, when a device that has obtained access to the bus through arbitration recognizes priority use and terminates its bus access out of order, it signals the end of its use of the bus. The arbitration supervisor generates a new arbitration period in response to this instruction. If the CPU is the device that generated the preemption signal requesting release of the bus, the CPU responds at the beginning of the arbitration cycle unlike other devices competing for bus access. At the beginning of an arbitration period, each other device competing for access to the bus enters its priority value on the arbitration lead. The CPU does not participate in this process at all. As the arbitration cycle begins, the CPU actually begins using the bus.

In an actually constructed embodiment of the invention, the minimum arbitration period is 300 nanoseconds.

However, a zero wait state bus cycle is less than 300 nanoseconds. Therefore, when the CPU is granted preemption, ie, gains access to the system bus, it can actually complete the cycle at the same time as the arbitration process.

Thus, the present invention provides the CPU with a means to allow preferential use of the system bus, which was previously distributed based on an arbitration mechanism.

Further, according to the present invention, when a CPU gains access to the system bus through its preemption signal, the CPU
A PU can initiate a bus cycle that can be completed while other devices contend for access to the bus.

That is, in one embodiment, the present invention provides a multi-bus microcomputer system that includes the following requirements.

a) a processor and cache subsystem connected by a CPU local bus; b) random access memory, arbitration supervisor and other functional units connected by a system bus; c) said CPU local bus. d) wherein said CPU local bus and said system bus are dedicated to arbitrating access to said system bus by at least some of said other plurality of functional units; e) a plurality of conductors, one of the plurality of conductors conveying a preemption signal; e) an input responsive to a CPU local bus cycle exceeding a minimum duration; said CPU local bus for generating a preemption signal which is effective in a functional unit having said access to limit the duration of access to said system bus;
Priority use signal generation swallow means with an output connected to the bus.

E. Embodiment FIG. 2 shows a typical microcomputer system to which the present invention can be applied. As shown, microcomputer system 10 includes several interconnected components. Specifically, the system unit 30 displays a monitor 2 (such as a conventional video display).
Connected to 0 to drive it. system unit 3
0 is also connected to input devices such as a keyboard 40 and a mouse 50. Output devices, such as a printing device 60, can also be connected to system unit 30. Finally, system unit 30 includes one or more disk drives, such as disk drive 70 . As explained below, system unit 30 includes keyboard 4
Input devices such as 0 and mouse 50 and disk drive device 7
In response to an input/output device such as 0, a signal for driving an output device such as a monitor 20 or a printing device 60 is supplied.

Of course, other conventional components can also be interactively connected to system unit 30, as known to those skilled in the art. In accordance with the present invention, microcomputer system 10 includes a cache memory subsystem (as specifically described below) that interconnects a processor, cache controller, and cache memory. - There is a bus, and the cache memory itself is connected to the system bus through a buffer. The system bus includes a keyboard 401 and a mouse 50.
, a disk drive 70, a monitor 201, a printer 60, and other input/output devices, and interacts with them. Further in accordance with the present invention, the system unit 30 includes a third micro channel (TM) architecture for interconnecting between the system bust and other output devices.
It can also include buses.

FIG. 1 shows a microcomputer according to an embodiment of the present invention.
FIG. 1 is a configuration diagram of a system. CPU local bus 230
(including data lines, address lines and control lines) is (80
Microprocessor 225 (such as 386), microprocessor 225 (such as 8238
5) cache control device 26
0 and random access cache memory 255
Make the connection. A buffer 240 is also connected to the CPU local bus 230. Buffer 240 is itself connected to system bus 250 and is connected to system bus 250.
50 also includes address lines, data lines and control lines. System bus 250 is between buffer 240 and another buffer 253. System bus 250 is
Bus control/timing device 265 and DMA controller 3
It is also connected to 25. Arbitration control bus 340 connects bus control/timing device 265 and arbitration supervisor 335 . Main storage device 350
is also connected to system bus 250. The main memory includes a memory controller 351, an address multiplexer 352, and a data buffer 353. These elements are included in the memory configuration section 361 as shown in FIG.
to 364 are interconnected.

Another buffer 267 connects system bus 250 and I10.
connected between buses 270; 10 bus 270 includes address lines, data lines, and control lines. I1
0 bus 270 along with display adapter 275 (used to drive monitor 20), clock 28
01 additional random access memory 285, R8232 adapter 290 (used for sequential I/O operations),
Printing device adapter 295 (which can be used to drive printing device 60), timer 300 . (Disk drive device 70
Various input/output adapters and other components are connected, such as a diskette adapter 305 (which cooperates with the computer), an interrupt controller 310, and a read-only memory 315. The buffer 253 connects to the Micro Channel (TM) bus 32, which is represented by a Micro Channel (TM) socket.
provides an interface between the system bus 250 and any functional bus, such as 0 or 0. Devices such as memory 331 may be connected to bus 320.

Figures 8-11 are useful in explaining the arbitration mechanism. Referring to FIG. 8, an arbitration supervisor 335 and a local arbitration unit 338 (representative of all local arbitration units) are shown. - In order for the device to transfer data, the system bus 25
0, local arbitration unit 336 receives and receives request signals from the particular device with which it is associated. The request signal is converted to a PREEMPT signal.

This signal is generated by the local arbitration unit and sent to the arbitration supervisor 335 and each local arbitration unit via the preemption line of the arbitration bus.

Note that in this particular embodiment of the invention, each priority line is OR'ed, so it is not important to arbitration supervisor 335 which particular device generated the request. Arbitration monitoring mechanism 335
is one or more local arbitration
)(
Generate the ARB/GRANT signal at the appropriate time determined by the LDA and +Refresh Memory signals.

HLDA is a single bus system, with one signal of the HLDA and IRQ (or HOLD) pair exchanged between the arbitration supervisor 335 and the CPU.

In a dual bus system, these signals are between the arbitration supervisors:82385.

When any device attempts to contend for use of system bus 250, that device generates a request signal to local arbitration unit 336 corresponding to its location. Local arbitration unit 336 is connected to /P on the arbitration bus.
Generates a priority use signal on the REEMPT line. Arbitration supervisor 335 then sends a signal on the arbitration bus to each local arbitration unit 336 at an appropriate time, as determined by the hold and refresh signals from the refresh controller, that the bus is available. ARP/GRANT +AR
Generate B state. In response to the ten ARB condition, each local arbitration unit 336 desiring access to system bus 250 issues an arbitration
Drive that priority level onto the appropriate line ARBO or ARBS of the bus. Then the system bus 25
Local arbitration requesting access to 0
Each unit 1~ compares its specified priority level with the priority level on the arbitration bus, and determines whether the priority level is the one on the arbitration bus.
If the level is lower than the second drive level, the bus will no longer be contested.

That is, at the end of the arbitration cycle,
Only one of the local arbitration units with the highest priority level during that arbitration cycle remains in contention for the bus and therefore receives and receives GRANT status from arbitration supervisor 335 via the ARBZGRANT line. gain control of the bus.

Referring now to FIGS. 9 and 10, more detailed circuitry of arbitration monitoring mechanism 335 is shown.

The arbitration monitoring mechanism 335 includes counters 31 to 34, an OR gate 35, an OR gate 36, a NAND
It includes a modified Johnson ring timing chain including gate 37, inverter 38 and OR gate 39. Assuming that the bus departs from an idle state where CPU 225 "owns" the bus but does not use it,
Circuit operation will be described below in conjunction with the timing diagram of FIG. In the above state, 't ARB/GRANT is active and at a low level, and arbitrage lane priority levels ARBO to ARB3 all have a value of 1.

Modified Johnson Ring Timing Chain O
+HL D via R gate 36 and NAND gate 37
It is held in a reset state by the A signal. /PREE when the device requires access to the bus.
MPT signal is activated. As shown in Figure 10, /
As a result of the PREEMPT signal going active, the output of the gate goes positive and the processor retention request (+PROCIR
Q) Represents a signal. +ARBO or +ARB3 so that the CPU 225 does not interfere with bus transfers by other devices.
The signal and +GRANT signal are input to the OR gate of FIG.

The +P ROCI RQ signal deactivates the +HLDA signal, which causes the reset signal (output from OR gate 36) to be removed from counters 31-34. As shown in FIG.
Note that T must become inactive. The -8O signal represents a write cycle and the S1 signal represents a read cycle. -CMD signal is -8O
or -81 after a certain time by the current bus mask. -CMD commands the slave device to input read data onto the bus during read cycles, and is activated during write cycles for validation of write data.

On the next (20 MHz) clock pulse, after +HLDA is deactivated, the output of counter 31 is set, causing the output of OR gate 39, which indicates the arbitration timing period, to go high (+ARP). The output of OR gate 39 remains high until the output of counter 33 goes low after the output of counter 34 goes high. This establishes a 300 nanosecond timing pulse for the ARB/GRANT signal.

The output from counter 34 remains set until the device initiates a bus cycle by activating -80 or -81. Its output is then reset and counters 31-34 are ready to begin timing again at the end of the current bus cycle. If no device requests bus service, the bus returns to an idle state and control returns to the processor. HLDA is reactivated and the bus is available for processor operations.

FIG. 3 shows an 80386 microprocessor such as a microprocessor 225.
The interconnection between the CPU and arbitration supervisor 335 is shown. The input and output signals provided to the right side of arbitration supervisor 335 are described in the aforementioned application. Specifically, the output signal ARP/GRANT indicates that the arbitration mechanism is in the arbitration state (
During that time, the devices contending for access to the system resource can enter their priority levels on the arbitration conductor) or in the granting phase (during which devices that have won access to the common resource can enter their priority levels to contest access to the common resource. This is a signal that specifies whether the resource can be used to the exclusion of other devices that were currently using the resource. Other input signals to the arbitration supervisor 335 are the PREEM signals already described.
It is a PT signal.

Finally, the input lines to arbitration supervisor 335, represented by ARB[0-31, are arbitration leads, which are driven by devices contending for access at their own priority level during the arbitration phase. The input/output connections on the left side of arbitration supervisor 335 are representative of a single bus.
80386 in microcomputer systems
It shows the interconnection with. signal) (with LDA) (RQ
(often referred to as HOLD) is a handshaking mechanism by which arbitration supervisor 335 rejects 80388 (IRQ) to request access to system resources. 8038f3 is the acknowledgment CI
(LDA) Then, the arbitration monitoring mechanism 335
can distribute access rights to resources. In a single bus microcomputer system, the CPU cannot be preempted for itself. This increases the undesirable possibility that the CPU will be locked out of common resources by devices that can burst.

FIG. 4 is a block diagram illustrating selected interconnections in a dual bus microcomputer system using an 80386 CPU and an 82385 cache controller. The input/output connections on the right side of arbitration monitoring mechanism 335 in FIG. 4 are the same as those in FIG. 3 and will not be described again. An important point in FIG. 4 is that in this case, since the 82385 cache controller sends and receives HRQ and HLDA signals, the supervision of the arbitration supervisory mechanism 335 is performed by the cache controller. In the absence of other devices, the 80386 CPU may be frozen from using common resources. The present invention provides such other mechanisms and, to a large extent, does so without affecting other devices accessing the common resource.

5 and 6 illustrate how signal CPREEMPT and its predecessors CPURE, Q are generated.

Referring first to FIG. 6, this logic can be considered part of cache controller 260.

This logic circuit is provided to generate a signal CPUREQ, which can be considered a control signal input to the control portion of buffer 240. The control signal CPUREQ is /
BUSCYC386, READYI, CLK, RESE
T and /C/M/I O&A31) are generated from the inputs shown on the left. The last signal is the decoded address to the coprocessor. Signal BUSCYC386
, READYI and / (/M/IO&A31), for example, when flip-flop 601 is set (by a high input on its D input), its output is high and the CPUREQ signal is low (active). This is an active low level signal.

In addition to flip-flop 601, the logic circuit of FIG. 6 includes an OR gate 602, three AND gates 603-605, and inverters 606-608.

In effect, the input to AND gate 603 detects 80386 cycles that extend beyond zero wait states but are not dedicated to the coprocessor. When this condition is detected, flip-flop 601 is set and cannot be set until clock time CLK2 when the condition ends. Gates 604 and 605 are CLK
is provided to reset flip-flop 601 when READYI is high and READYI is (active) low. This state occurs when the CPU bus
when the cycle is complete.

A CPU local bus cycle that extends beyond zero wait states (and is not a coprocessor-only cycle) is:
These are cycles that require access to the system bus. Therefore, under these circumstances, CPUREQ becomes active, ie, goes to a low level. The effect of this signal is shown in FIG.

FIG. 5 shows logic circuitry associated with system bus 250. FIG. As shown in Figure 5, the control portion of buffer 240 (driven by the same signals shown in Figure 6)
It has an output line CPUREQ.

CPUREQ is the input to gate 501 and the output of gate 501 /CPREEMPT is actually the PREEMPT signal generated by the 80386. As can be seen in FIG. 5, the signal /CPREEMPT is fed to the priority use conductor, which is one of the input lines to the arbitration supervisor 335 (see FIGS. 3 or 4).
. Signal /CPREEMPT is connected to gates 501 to 503
are generated by the logic circuit shown in FIG.

The second input to gate 501 is the output of gate 503, one of whose inputs is the ARB/GRANT signal (same as the output of arbitration supervisor 335). Another input is ENCPUPREEMPT. The latter is the output of 80386. When inactive, this signal prevents /CPREEMPT from becoming active.

That is, when ENCPUPREEMPT is inactive, 8038B cannot be preempted. ENC: PUPRE
EMPT is controlled by user configurable switches or software switches depending on the requirements of other system equipment and/or software. Under normal circumstances, ENCPUPREEMPT is active and therefore 80386 can be preempted. When ARB/GRANT indicates that the arbitration process is in the grant phase (ENCPUPREEMPT is active), the output of gate 503 becomes active. The active output of gate 503 is active CPUREQ
Together with this, it is possible to generate an activity/CPREEMPT. Gate 503 prevents the generation of activity/CPREEMPT during the arbitration phase and enables activity/CPREEMPT only during the grant phase of the arbitration process. Gate 502 is used to monitor the state of the arbitration conductors and indicates that all conductors are high (active) and no other device is arbitrating to the bus, i.e. the CPU or owning a common resource. Activities/CPREE
Prevents the generation of MPT.

Therefore, by the logic circuit shown in FIGS. 5 and 6,
If the arbitration mechanism is in its granting phase during cycles of the CPU local bus that are not dedicated to the coprocessor and extend beyond a minimum duration (zero latency),
The CPU is used preferentially.

The effect of this preferential use will be explained later in connection with FIGS. 78-7E.

Figures 78 to 7E are from the aforementioned Japanese Patent Application No. 632217.
It is similar to Figure 4 of No. 7 and shows the following.

1) The burst device uses the system bus (a
-d), 2) Preferential use of the device by a normal device using the PREEMPT signal (b-h), 3) /CPREEMP
The CPU acquires the bus using the T signal (k-o)
, 4) Arbitrate for use of the bus by other devices at the same time that the CPU uses the bus (m).

Specifically, as an example, assume that a burst type device has gained control of the system bus as shown in FIG. 7D (a). Other devices along the system bus are PR
Upon asserting EEMPT (b), the bursting device currently under control completes its current transfer as shown in FIG. 7C. A bursting device relinquishing control of the system bus when the current transfer is complete is shown in Figure 7 (d).
) remove the burst signal from the burst line. This burst device performs the following arbitration
Does not participate in the cycle. Next, the arbitration monitoring mechanism 335 puts ARB/GRANT into the ARB state ((e) in FIG. 7A). This same transition represents the beginning of another arbitration cycle, with system bus arbitration beginning at (f) in FIG. 7B.

After the ARB/GRANT signal goes low, the 7th A
As shown in Figure (g), control of the system bus is given to the new device. A new device that gains control of the system bus removes its PREEMPT signal in response to the grant signal, as shown in FIG. 7E (h).

After a while, the CPU shown in Figures 7A to 7E
Based on the conditions reflected on local bus 230, C
The PU asserts /CPREEMPT reflected in PREEMPT ((k) of Figure 7E). As already explained, as a result, a new arbitration cycle begins as shown in FIG. 7A (1). As shown in Figure 7A, the arbitration cycle is (1-o)
Extends from. During this arbitration cycle,
The CPU actually utilizes the system bus. At the beginning of the cycle, the CPU sends its PREEMPT signal (7th
Release the assertion (n) in Figure E.

While the CPU is using the system bus, other devices contending for access to the system bus will arbitrate for its resources beginning at (m) in FIG. 7B. At the end of a CPU cycle, when the CPU has finished using the system bus (0), a new arbitration is completed;
Immediately thereafter, other devices (if any are contending for access to the system bus) can utilize the resource for the period beginning at (0) in FIG. 7A.

The /CPREEMPT signal is active only when a cPU bus cycle extends beyond a predetermined duration (eg, beyond a zero wait state). During the arbitration phase (ARB/GRANT is high), the CPU
In the cache control device 260, the monitoring mechanism 335
Bringing Q to a low level releases the hold state and allows one or more cycles to run.

Completion of a CPU cycle in which the system bus can be used using the preemption mechanism is detected by READYI being active and CLK going high.

The logic circuit of FIG. 6 causes flip-flop 6o1 to be reset and CPUREQ to be inactive under these conditions.

The logical formula quoted above is reproduced below. In this specification, symbols have the meanings shown below.

10t / & + 】Shi-Kai denial Registration order, equal combinational terms, equal Logical AND logical sum ARB [0 3 pieces ARB/GRANT / (/M/I O&A3 1) /CPREEMPT /CPtJREQ logic signal arbitration· Bus pits arbitration· Start/end of cycle stipulates completion decoded numerical operations coprocessor ad response See Figure 5 See Figure 6 ENCPUPREEMPT PREEMPT CPU/CPRE EMPT generation ability enable or disable programmable bit Arbitration channel through request use /CPREEMPT can be generated by Amended in this application as do.

Logical Formula %Formula %(1) In the above logical formula, the following signals are described or referenced in the cited Intel publications.

ADS BADS BRDYEN BREADY (BW/R) Actually called BW/R.

The parentheses indicate that the entire term is one signal. used to indicate that there is It will be done.

L.K. READYO RESET WBS (W/R) Actually called W/R.

The parentheses indicate that the entire term is one signal. used to indicate that there is It will be done.

ADS, when active, connects the CPU local bus 23
Indicates a valid address on 0. BADS indicates a Th-effective address on system bus 250 when active. BRDYEN precedes the READY signal by 8238
This is the output of 5. BREADY is system bus 25
Ready signal from 0 to CPU local bus 230. BW/R defines system bus 250 writes or reads. CLK is a processor clock signal synchronized with processor 225. READY
O is one of the ready signals and is the other output of the 82385. RESET is self-explanatory. WBS indicates the state of the write buffer. (W/R) is CPU local bus 23
Communication write or read signal for 0.

The following signals are defined by equations (1)-(11).

BREADY385 Br2 BtJFWREND BUSCYC385 BUSCYC386 CPUNA LEAB l5SI PIFECYC385 PIFECYC386 CPUREADY With respect to the defined signals, the signal NCA1NAGACHE
, READYO387 and RDY387PAL are described or referenced in the cited Intel publications.

BREADY385 is a signal like BREADY,
In one example actually constructed, 64 was modified to accommodate a cache.

Br3 reflects the state of system bus 250. State BT2 is the state defined in the cited Intel publication.

BUFWREND represents the end of a buffered write cycle.

BUSCYC385 also reflects the state of system bus 250. This signal indicates the bus status BT11BTI, BT
Wealth level in IP, bus state BT2, BT2P1B
T2I is low level (these are the bus states referenced in the cited Intel publication).

BUSCYC 388 is high during CPU local bus 230 states TI, T1, TIP, and T21;
2 is a low level. If T2I does not occur first, T2P is also at a low level.

CPUNA is a signal that causes the 80386 to perform pipelined operation.

LEAB for recorded writes (buffer 24
0) is the latch enable signal.

MISSI defines the first cycle of a dual cycle for handling 64-bit reads to cacheable devices when active.

PIPECYC385 is active during BTIP (which is a dual cycle referenced in the cited Intel publication).

PIPECYC386 is N CPU local bus 23
During the 0 state TIP it is at a low level.

CPUREADY is the ready input to 8038(3).

NCA is a signal generated by decoding address components on CPU local bus 230;
When active, reflects non-cacheable accesses. Cacheability is determined by tag components (A31 to A17), which are programmable information that define which tags indicate cacheable rather than non-cacheable addresses.

NACACHE is a signal similar to the BNA signal. B.N.
A is a system generated signal requesting the next address from CPU local bus 230 and is referenced in the cited Intel publication.

The only difference between NACACHE and BNA is that BNA is created for caching at 32, while NACACHE is created for caching at 64.

If the cache memory is 32 as cited in the Intel publication, the NACACH referenced herein
A BNA signal can be used instead of an E signal.

READYO387 is the ready version of the 80387 numerical coprocessor.

RDY387PAL is the output of an external logic circuit that is used when the math coprocessor is not installed to prevent system operation from being hampered in the absence of the 80387 math coprocessor.

Effects of the F1 invention By using the present invention, the 80386 processor and the 8238
It is clear that in a dual-bus microprocessor system using a five-channel controller, the processor can conditionally preempt the system bus under certain circumstances. Specifically, for a local bus cycle that exceeds a predetermined duration, the processor determines that another user is contending for access to the resource and that a preemption option is available (ENCPUPREEM).
/CPREEMPT can be asserted under the condition that /CPREEMPT). However, when preemption is enabled (signaled to the processor by the arbitration supervisor), two events occur simultaneously. The first event is that the processor accesses the system bus.

During the processor's access, other competing users are in the arbitration stage, so this access does not interfere with other potential bus users. That is, during a processor's access to the system bus, other users can arbitrate for access to the second grant stage after the processor uses the bus. Therefore, by using the present invention, the processor:
The system bus is now available even if other user devices are contending for access to the bus at the same time.

The overlap between the arbitration phase (initiated by other devices) and the use of the bus by the processor increases bus utilization and efficiency.

[Brief explanation of the drawing]

FIG. 1 shows a microcomputer according to an embodiment of the present invention.
FIG. 1 is a configuration diagram of a system. FIG. 2 is an explanatory diagram of a typical microcomputer system that utilizes the present invention. FIG. 3 is an illustration showing how to connect an arbitration supervisor and a CPU according to a single bus microcomputer system. FIG. 4 is an explanatory diagram illustrating a method of interconnecting an arbitration monitoring mechanism, a CPU, and a cache control device according to the present invention. FIG. 5 is a circuit diagram of a device associated with a CPU for generating a priority use signal. FIG. 6 is a circuit diagram of a logic circuit accompanying the CPU for generating the CPUREQ signal used when the CPU generates the priority use signal. 7A-7E are timing waveform diagrams illustrating multiple arbitration and grant cycles. FIG. 8 is an explanatory diagram showing the relationship between the central arbitration monitoring mechanism 335 and arbitration mechanisms 336 attached to other devices. 9 and 10 show the arbitration monitoring mechanism 3
35 is a configuration diagram. FIG. 11 is a timing waveform diagram illustrating the operation of FIG. 8. 10...Microcomputer system, 20.
... Monitor, 30 ... System unit, 40
...Keyboard, 50...Mouse, 60...
-Printing device, 70...disk drive device. Applicant International Business Machines Corporation Representative Patent Attorney Takashi Tonmiya (1 other person)

Claims (6)

[Claims] (1) a processor and a cache subsystem connected by a local bus; a random access memory, an arbitration supervisor, and a plurality of functional units connected by a system bus; the local bus and the system bus; means for connecting the local bus and the system bus;
a plurality of conductors dedicated to arbitrating access to the system bus by at least some of the plurality of functional units, one of the plurality of conductors carrying a preemption signal; and a minimum duration. having an input responsive to exceeding the local bus cycles and generating a preemption signal which, when received, is effective in limiting the duration of said access in a functional unit having access to said system bus; a multi-bus microcomputer system comprising: means for generating a priority use signal having an output connected to said local bus; (2) The arbitration monitoring mechanism includes means for generating an arbitration cycle regulation signal, means for preparing an arbitration stage in response to the priority use signal, and responsive to a signal indicating termination of use of the bus by the current bus user. means for initiating an arbitration phase by
and means for signaling a new arbitration stage to said processor. (3) While the preemption signal is generated for immediate access to the system bus, the processor is responsive to the signal from the arbitration supervisor indicating a new arbitration stage. ) Multiple bus microcomputer system described in paragraph 2. (4) The priority use signal generating means, in response to a programmable signal, permits generation of the priority use signal in one state of the programmable signal, and generates the priority use signal in the other state of the programmable signal. A multi-bus microcomputer system according to claim (3), which prohibits the following. (5) an optional bus connected to the local bus through the system bus and the connecting means, wherein devices connected to the optional bus arbitrate for access to the system bus; and responsive to said preemption signal from said preemption signal generating means for terminating access to the bus in response to receipt of said preemption signal. Claim No. 1
) Multiple bus microcomputer system described in paragraph 2. (6) Establishing an arbitration stage for arbitrating access among a plurality of devices when the arbitration cycle regulation signal is in a predetermined state, and allowing the winning device in the arbitration stage to use the system bus. The plurality of conductors include an arbitration cycle definition conductor carrying an arbitration cycle definition signal to establish a granting phase of the system, the plurality of conductors including an arbitration cycle definition conductor carrying an arbitration cycle definition signal, the processor controlling the system in the arbitration phase immediately following generation of the preemption signal. A multiple bus microcomputer system according to claim 1, including means for accessing a bus.