NO176038B - Multi-bus microcomputer system with bus arbitrage - Google Patents

Description

The present invention relates to bus arbitration by a multi-bus microcomputer of the type stated in the introduction to claim 1.

Background information on the 80386 microprocessor, its characteristics, and its use in microcomputer systems including flash memory subsystems is described in the Intel Corporation publication "Introduction to the 80386", April 1986 and in the 80386 Hardware Reference Manual (1986). The characteristics and operational performance of the 82385 cache controller are described in Intel Corporation *s publication "82385 High Performance 32-Bit Cache Controller" (1987).

New Electronics, vol. 20 No. 7, March 1987, pages 30-33, describes the use of an 80386 processor and an 82385 flash memory controller in a dual bus microcomputer system.

Furthermore, DK-165077 describes a device in a computer system that comprises several processors/subsystems to monitor and provide access to a bus, where lower priority processors are given access to the bus when the highest priority processor is not using the bus. This device is of the same type as stated in the introduction to claim 1.

Microcomputer systems that include a high-speed storage subsystem are architecturally very different from microcomputer systems without high-speed storage subsystems. Microcomputer systems with a high-speed storage subsystem operate as dual-bus devices. In microcomputer systems with a cache subsystem, there is specifically a first bus (referred to as the CPU local bus) that interconnects the CPU cache and the cache controller. Other devices are connected to another bus (system bus). Such other devices include e.g. main storage, I/O devices and auxiliary devices. In addition to the above-mentioned devices, the system bus can also be connected to the quick storage controller. The fast storage subsystem relieves the system bus of a larger part of the storage access that would otherwise be performed by the system bus without the fast storage subsystem. That is to the extent that the CPU can obtain information from the cache for that particular cycle, the CPU does not require access to the system bus. Other devices can consequently use the system bus for other operations during the same time period. This is expected to result in a significant reduction in the system bus cycles actually used by the CPU. The cache controller is usually connected to both the system bus and the CPU local bus and one of the functions of the cache controller is to monitor arbitrary control (supervisor) which in single-bus systems has been monitored by the CPU.

An available flash memory controller, the 82385 flash memory controller, has the ability to operate in a master mode or a slave mode. When the 82385 RAM controller is operated in the master mode and oversees the arbiter control, there is no longer any mechanism for the CPU to contend for the system bus resources.

It is therefore an object of the present invention to provide a mechanism where a CPU of a multi-bus microcomputer system with a fast storage control element, which monitors the arbitration control (monitoring), can access the system bus source distributed by the arbitrary mechanism.

The arbitrary monitor responds to arbitrary request signals that are connected in common from multiple devices. When the arbitrary monitor recognizes that one or more devices have requested the shared resource, it signals the beginning of an arbitrary period by changing the state of a leader (ARB/GRANT) accessible to all requesting devices. When the requesting devices see the state of the changed leader so as to signal the beginning of an arbitrary period, the devices generate signals corresponding to their priority levels and drive several arbitrary leaders dedicated to this function with those signals. The connection between the number of devices and arbitrary conductors is arranged so that the conductors assume the priority value of the highest priority circuit that drives the arbitrary conductors. Each device can therefore recognize, by comparing the priority value of the arbitrary conductors with its own priority value, whether there is any higher priority device requesting access to the bus. At the end of a predetermined arbitrary period, the ARB/GRANT manager changes state. This begins the grant period during which the requesting device, whose priority value was the priority value of the arbitrary conductors, assumes control of the common source to start a bus cycle.

There is still another conductor dedicated to a PREEMPT signal that can be generated to force a device that has received access to the system resource to terminate its access. A device that has received access to the system source and uses that source upon recognition of a proven PREEMPT is thus required to initiate an order termination of its use of the system source. When the device which is thus preempted ends its use of the common source, the arbitrary monitor begins a new arbitrary period as described above.

In the case of a microcomputer system with a flash memory subsystem, the CPU periods for accessing flash memory (and thus not requiring access to the system bus) are periods of minimal duration or zero wait period states. When CPU periods extend beyond this minimum, they signal the CPU about demands for the system bus. CPU periods, longer than the minimum duration, thus signal to the CPU that there is a need for the system bus, the common source.

In accordance with the invention, the CPU is provided with means for generating a PREEMPT signal which will cause any device which has gained access to the bus through the arbitration mechanism to terminate the access already described. As described later, the CPU's generation of PREEMPT is controlled by detecting a CPU period with a duration longer than necessary for a fast storage address.

However, the CPU's use of the system resource is arranged to save as much time as possible. Specifically, when a device that has been granted access to the bus via an arbitration ring recognizes a PREEMPT and initiates an orderly termination of its bus access, it signals the termination of use of the bus. The arbitration monitor responds to this indication by generating a new arbitration period. If the CPU was the device that had generated PREEMPT to request release of the bus, it would react differently at the start of the arbitrary period than if another device requests bus access. At the beginning of the arbitration period, each of the other devices requesting access to the bus places its priority value on the arbitrators. The CPU does not enter into this process at all; but at the beginning of the arbitration period the CPU really begins using the bus.

In one embodiment of the invention that has been constructed, the minimum arbitration period is 300 nanoseconds. However, a zero wait state bus period is less than 300 nanoseconds. Whenever the CPU preempts and thereby gains access to the system bus, it can therefore complete a period completely with the arbitration process.

According to the present invention, a multi-bus microcomputer system of the kind stated in the introduction and whose characteristic features appear in claim 1 is provided. Further features of the invention appear in the other independent claims.

In what follows, the invention will be described in more detail with reference to the drawings, where:

Fig. 1 shows a total overview of a typical microcomputer system that can use the present invention. Fig. 2 shows a detailed block diagram of the main components of a typical microcomputer system employing the present invention. Fig. 3 shows how the arbitration monitor and CPU are connected in accordance with a single-bus type microcomputer system. Fig. 4 shows how the arbitrary monitor, CPU and fast storage controller are connected together according to the present invention. Fig. 5 shows the device connected to the CPU to generate a

PREEMPT signal.

Fig. 6 shows the logic associated with the CPU to generate a signal CPUREQ which is used to generate a PREEMPT signal by means of the CPU. Fig. 7 shows a timing diagram of several arbitrary and permission periods, one of which is given access to the system bus with a generic device and another during which access to the system bus is provided to the CPU via a PREEMPT signal. Fig. 8 shows the relationship between the central arbitration tree monitor 335 and the arbitration device 336 connected to other devices. Figs. 9 and 10 collectively show a block diagram of an arbitrary monitor 335. Fig. 11 shows a timing diagram to explain the operation shown

on fig. 8.

Fig. 1 shows a typical microcomputer system in which the present invention can be used. The microcomputer system 10 includes a number of components which are connected together. Specifically, a system unit 30 coupled with and operating a monitor 20 (such as a conventional video display device). The system 30 is also connected with input devices such as a keyboard 40 and mouse 50. An output device, such as the printer 60, may also be connected to the system unit 30. The system unit 30 may include one or more disk drives, such as disk drive 70. Which will be described below, system unit 30 responds to input devices such as keyboard 40 and mouse 50, and input/output devices such as disk drive 70 to provide signals to drive output devices such as monitor 20 and printer 60. Naturally, other and conventional components may be connected to system unit 30 for cooperation with this. In accordance with the present invention, the microcomputer system 10 (which will be described in more detail below) includes a fast storage subsystem so that there is a CPU local bus that connects a processor, a fast storage controller and a fast storage which is itself connected via a buffer with a system bus. The system bus is interconnected with and interacts with the I/O devices such as the keyboard 40, the mouse 50, the disk drive 70, the monitor 20 and the printer 60. In accordance with the present invention, the system unit 30 also includes a third bus including a Micro Channel architecture (Micro Channel is a trademark of IBM) for connection between the system bus and other input/output devices.

Fig. 2 shows a high-level block diagram of various components of a dual-bus microcomputer system. A CPU local bus 230 (which includes data, address and control components) provides connection of a microprocessor 225

(such as an 80386 processor), a cache controller 260 (which may include an 82385 cache controller) and a direct store 255. Also connected to the CPU local bus 230 is a buffer 240. The buffer 240 is itself connected to the system bus 250, which also includes address, data and control components. The system bus 250 extends between the buffer 240 and a further buffer 253.

The system bus 250 is also connected to a bus controller and a timing element 265 and a DMA controller 325. An arbitrary control bus 340 connects the bus controller and the timing element 265 and the arbitrary monitor 335. The main storage is also connected to the system bus 250. The main storage includes a storage control element 351, an address multiplexer 352 and a data buffer 353. These elements are connected together with storage elements 36 via 364, as shown in fig. 2.

A further buffer 267 is connected between the system bus 250 and a plan bus 270. The plan bus 270 includes address data and control components respectively. Connected along the plane bus 270 are various I/O adapters and other components, such as a display adapter 275 (used to drive the monitor 20), a clock 280, an additional direct storage 285, an RS 232 adapter (used for serial I/O operations), a printer adapter 295 (which may be used to drive the printer 60), a clock 300, a floppy disk adapter 305 (interoperating with the disk drive 70), an interrupt controller 310, and a read buffer 315. The buffer 253 provides an interface between the system bus 250 and an option bus such as the Micro Channel bus 320 represented by the Micro Channel sockets. Devices such as bearing 331 may be connected to bus 320.

Fig. 8-11 is useful for describing the arbitrary mechanism. With reference to fig. 8, the relationship between the arbitrary monitor 335 and a local arbitrary unit 336, which represents all local arbitrary units, shall be described. When a device wants access to the system bus 250 to transfer data, generally a local arbitrary unit 336 will receive a request signal from a particular device, to which the arbitrary unit is in relation. The request signal is transformed into a PREEMPT signal which is generated by the local arbiter and sent to the arbitrary monitor 335 and each of the local arbiters over the PREEMPT lines of the arbitrary bus. It should be noted that in the particular embodiment of the invention that the PREEMPT lines are connected via OR gates and are thus irrelevant to the arbitrary monitor 335 as a special device generating the request. Arbitrary monitor 335 generates the ARB/GRANT signal at a suitable time then determined by HLDA and the +REFRESH storage signal from a refresh controller (not shown) which should be well known to those skilled in the art, in response to a /PREEMPT signal from one or more of the local arbitrators 336. HLDA is a signal to the pair HLDA and HRQ (or HOLD) which, in the one-bus system, was exchanged between the arbitrary monitor 335 and the CPU. In the case of dual-bus systems, these are signals between the arbitrary monitor and the fast storage controller, shown at reference numeral 260 in FIG. 2.

Thus, when one of the devices wishes to request use of the system bus 250, a request signal is generated to the corresponding local arbitrary device 336 which. then generates a /PREEMPT signal across the /PREEMPT line of the arbitrary bus. At an appropriate time when the bus becomes available, then determined by the HOLD and +REFRESH signal from the refresh controller, the arbitrary monitor 335 generates the +ARB state of the ARB/GRANT signal over the arbitrary bus to each of the local arbitrator devices 336. In response to the +ARB state drives each local arbitration device 336 that wants access with the system bus 250 its priority level to respective lines ARB0-ARB3 on the arbitrary bus. Each of the local arbiter devices seeking access to the system bus 250 compares its designated priority level with the priority level of the arbitrary bus and itself exits the request for the bus in the event that the priority level is lower than that which has been driven on the arbitrary bus. Thus, at the end of the arbitrary period, only the local arbiter device that has the highest priority level during the arbitrary cycle remains to request the bus and thus gains control of the bus when the GRANT state is received from the arbitrary monitor 335 over the ARB/GRANT line.

Figs. 9 and 10 show in more detail a circuit for describing the arbitrary monitor 335. The arbitrary monitor 335 includes a modified Johnson ring timing chain including counters 31 to 34 and the OR gate 35, OR gate 36, ENOUGH gate 37, inverter 38 and OR gate 39. Assuming that the bus begins at an idle state with the CPU 225 "owning" the bus but not using it, the circuit operation will be described hereinafter in connection with the timing diagram of FIG. 11. The above state is ARB/GRANT active low and the arbitrary-priority level ARBO to ARB3 would all have a value equal to one. The modified Johnson ring timing chain is then kept reset by the +HLDA signal via the OR gate 36 and the NOT gate 37. When a device needs to access the bus the /PREEMPT signal is activated. As shown in fig. 10, the /PREEMPT signal becoming active results in the output of the gate going positive, representing a PR0CESS0R HOLD REQUEST (+PR0C HRQ) signal. The +ARB0 to +ARB3 signal and a +GRANT signal are also fed to the Or gate of fig. 10 to ensure that the SPU 225 will not interfere with bus transmissions by other devices. The +PR0C HRQ signal results in a disable +HLDA which results in the reset signal (output of OR gate 36) being removed from counters 31 to 34. It should be noted that inputs -SO, -Sl, -CMD and -BURST must be inactive in order for +HLDA to remove the reset signals from the above-mentioned counters 31 to 34, as shown in fig. 11. The -SO signal represents the WRITE cycle, and

The -Sl signal represents the READ cycle. The -CDM signal is generated by the running bus master a certain time period after -SO or -Sl. During the READ cycle, CMD instructs the slave device to place READ data on the bus and i

during WRITE cycles, -CMD is enabled to validate WRITE data.

On the next (20 MHz) clock pulse, after +HLDA is disabled, the counter 31 output is set to cause the output of OR gate 39 to go high (+ARB), indicating an arbitrary time period. The OR gate 39's output remains high until the output of counter 33 goes low some time after the output of counter 34 has gone high. This establishes a 300 nanosecond time pulse for the ARB/GRANT signal. The output for counter 34 remains set until the device begins a bus cycle by either activating -SO or -S1. The output is then reset and counters 31 to 34 are ready to begin timing at the end of the current bus cycle. If no device requests bus service, the bus returns to the idle state and control is returned to the processor. HLDA is reactivated and the bus is now available for processor operations.

Fig. 3 shows the interaction between an 80386 CPU, such as the microprocessor 225, and the arbitrary monitor 335 in a one-bus microcomputer system. The output signal ARB/GRANT/ from the supervisor is the signal that defines whether the arbitrary mechanism is in the arbitrary state (during which the devices request access to the system resource to place their priority level on the arbitrary leaders) or in a permission phase (where the device that gets access to the shared resource can use that resource for excluding other devices that have requested access). Another input signal to the arbitrary monitor 335 is the PREEMPT signal which has already been described. The input to the arbitrary supervisor 335 represented by ARB0-3 is the arbitrary manager which during the arbitrary phase is operated by devices requesting access for their own priority levels. The input/output connections on the left side of the arbitrary monitor 335 show their connection with the 80386 processor of a typical one-bus microcomputer system. The signals HLDA and HRQ (sometimes referred to as HOLD) are

"handshake mechanisms" by which the arbitrary monitor 335 can request access to the system resource to exclude the 80386 processor (HRQ). When the 80386 processor acknowledges (HLDA) then the arbitrary monitor 335 can grant access to the source. In single-bus microcomputer systems, the CPU cannot preempt (PREEMPT) for its own part. This entails unwanted potential for the CPTJ to look for the common source of a device that is allowed to detach. Fig. 4 shows a block diagram of selected interconnections of a dual-bus microcomputer system using the 80386 CPU and an 82385 flash memory controller. The input/output connections on the right side of the arbitrary monitor 335 in FIG. 4 is identical to those in fig. 3 and will not be described again. The important point shown in fig. 4 is that the monitor of the arbitrary monitor 335 is now performed by the 82385 flash controller since it is the element to which the HRQ and HLDA signals are applied. In the absence of other devices, the 80386 CPU could be prevented from using the common source. The present invention provides the second mechanism and does so to a large extent without interfering with other devices' access to the common source. Fig. 5 and 6 together show how the signal CPREEMPT, and its predecessor CPUREQ, are generated.

With reference to fig. 6, the logic there can be considered as part of the flash storage controller 260. The logic is arranged to generate the signal CPUREQ which can be considered as a control signal passed to the control part of the buffer 240. The control signal CPUREQ is developed from the input signals shown to the left including /BUSYCYC 386, READY, CLK, RESET and /(/M/10 & A31). The last signal is the decoded address of the coprocessor. The signals BUSYCYC 386, READYI and /(/M/10 & A31) are active low signals so that e.g. when flip-flop 601 is set (by a high input signal at its D input), its output goes high and the CPUREQ signal goes low (active). In addition to the flip-flop 601, the logic of FIG. 6 an OR gate 601, three AND gates 603-605 and inverters 606-608.

The inputs to the 0G gate 603 detect an 80386 processor period that extends past the zero wait state and that is not at the same time a period designated for the coprocessor. As soon as the condition is detected, the flip-flop 601 is set, and can only be reset at a clock time CLK2 when the condition has ended. Gates 604 and 605 are arranged to reset flip-flop 601 when CLK goes high and READY (active) goes low. This condition occurs when a CPU bus period has completed.

A CPU local bus period that extends past the zero wait state (and which is also not a coprocessor dedicated period) is a period that requires access to the system bus. Accordingly, under these circumstances, CPUREQ becomes active, i.e. goes low. The effect of this signal is shown in fig. 5.

Fig. 5 shows logic connected to the system bus 250. As shown in Fig. 5, the control element of the buffer 240 has an output signal CPUREQ (which is driven by the same signal shown in Fig. 6). The CPUREQ signal is an input signal to a gate 501 whose output signal /CPREEMPT is actually a PREEMPT signal generated by the 80386 processor. As shown in fig. 5, the signal /CPREEMPT is connected to the PREEMPT conductor which is one of the inputs to the arbitrary monitor 335 (cf. Fig. 3 or 4). The signal /CPREEMPT is generated by the logic shown in fig. 5 including ports 501-503. A second input signal to gate 501 is the output signal to gate 503, one of whose inputs is the ARB/GRANT signal (identical to the output signal of arbitrary monitor 335). The second input signal is ENCPUPREEMPT. The latter is an output signal to the 80386 processor. When inactive, this signal will inhibit the /CPREEMPT signal from becoming active. When the ENCPUPREEMPT signal is inactive the 80386 processor cannot execute

PREEMPT. The ENCPUPREEMPT signal may "be controlled using a tunable switch or a software switch depending on the requirement of other system devices and/or software. Under normal conditions, ENCPUPREEMPT will become active, thus preparing the 80386 processor for PREEMPT. When ARB/GRANT / indicates the arbitrary process is in an enable phase (and ENCPUPREEMPT is active) then the output to gate 503 will become active. An active output to gate 503 added together with an active CPUREQ will enable generation of an active /CPREEMPT. Gate 503 will prevent the generation of a active /CPREEMPT signal during the arbitrary phase, and only allows an active /CPREEMPT signal during the permit phase of the arbitrary process.Port 502 is used to monitor the state of the arbitrary conductors and will prevent the generation of an active /CPREEMPT signal if all the conductors are (actively) high, indicating that other devices are not in the arbitrary phase of the bus, i.e. the CPU has the common source.

Using the logic shown in fig. 5 and 6, for the period on the CPU local bus that is not dedicated to the coprocessor and that extends past a minimum duration (the zero wait state), the following CPU may perform PREEMPT, and will perform PREEMPT if the arbitrary mechanism is in its permit phase. The effect of this PREEMPT execution will now be described in connection with fig. 7A-7E.

Fig. 7A-7E show:

1) use of the system bus using a burst device (a-d), 2) PREEMPTING that device using a typical device using the PREEMPT signal (b-h), 3) polling the bus using the CPU via use of the /CPREEMPT signal (k-o), and 4) concurrently with the use of the bus by the CPU, arbitrating for use of the bus by another device (m).

For the sake of illustration, it is assumed that a burst mode device has been given control of the bus as shown (a) in fig. 7D. When another device along the system bus asserts PREEMPT (b), the burst device in control completes its transmission as shown (c) in FIG. 7C. Upon completion of the ongoing transfer, the burst device relinquishing control of the system bus removes its burst signal from the burst line as shown at (d) in FIG. 7D. This burst device will not participate in the next arbitrary period. The arbitrary monitor 335 then applies ARB/GRANT/ to the ARB state (e) of FIG. 7A. The same transition represents the beginning of another arbitrary period and the system bus arbitration begins at (f) in FIG. 7B. After the ARB/GRANT signal goes low, control of the system bus is given to the new device as shown at (g) in FIG. 7A. The new device which has been controlled by the system bus then removes the PREEMPT signal in response to the GRANT signal as shown at (h) in fig. 7E.

Sometime later, in the example of fig. 7A-7E and based on states reflected on the CPU local bus 230, the CPU will. confirm the /CPREEMPT signal reflected in PREEMPT (k) in fig. 7E. As already mentioned, this will result in a new arbitrary period that begins as shown (1) in fig. 7A. The arbitrary period, as shown in fig. 7A, extends from (1-o). During the arbitrary period the CPU uses the system bus and at the beginning of that period the CPU deasserts its PREEMPT signal (n) in fig. 7E. During the CPU's use of the system bus, other devices may request access to the system bus arbitrarily for that source beginning at (m) in FIG. 7B. At the end of the CPU period, when it has finished using the system bus (o), a new arbitrary period has been completed so that immediately thereafter a further device (if any requests access to the system bus) can use that resource for the duration beginning at (o) in fig. 7A.

The /CPREEMPT signal is active only when a CPU bus period extends past a predetermined duration (past the zero wait state, for example). During the arbitrary phase (ARB/GRANT/high), the CPU cache controller 260 is released from the hold state by the watchdog 335 which waives the HRQ and is allowed to run for one or more periods.

The completion of a CPU period, allowed to use the system bus using the PREEMPT mechanism, is detected by READY active with CLK high. Using the logic of fig. 6, and under these conditions, the flip-flop 601 is reset and CPUREQ becomes inactive.

The logic equations that have been referred to above are shown below. In this context, the following symbols are indicated with their meaning:

In the preceding logic equations, the following signals are described or referred to in the cited Intel publications:

ADS

BATHROOMS

THE BRIDGE

BREADY

(BW/R) referred to as BW/R where the brackets are used for

to indicate that the entire expression is a signal.

CLK

READY0

RESET

WBS

(W/R) is usually referred to as W/R as the parentheses are used to indicate that the entire expression is a signal.

ADS, when active indicates a valid address on CPU local bus 230. BADS, when active indicates a valid address on system bus 250. BRDYEN is an output signal to the 82385 RAM controller that precedes the READY signals. BREADY is a ready signal from the system bus 250 to the CPU local bus 230. BW/R defines a system bus 250 write or read. CLK is a processor clock signal that is in phase with the processor 225. READY0 is another output signal to the 82385 latch controller in the ready signal line. RESET is back position. The WBS indicates the state of the write buffer.

(W/R) is the conventional write or read signal for the CPU local bus 230.

The equations (l)-(ll) define:

BREADY385

BT2

BUFWREND

BUSCYC385

BUSCYC386

CPUNA

LEAB

MISS

PIPECYC385

PIPECYC386

CPUREADY

expressed in defined signals, the signals describing or referring to the cited Intel publications and NCA, NACACHE, READY0387 and RDY387PAL.

BREADY385 is a signal like BREADY which is an embodiment modified to accommodate a 64K flash store. In the case of a 32K flash drive (as recommended by the manufacturer), BREADY can be used instead of BREADY385.

BT2 shows the state of the system bus 250. The state BT2 is a state defined in the cited Intel publications.

BUFWREND constitutes the end of a buffered write period.

BUSCYC385 also shows the state of system bus 250. It is high for bus states BTI, BT1, BT1P and low for bus states BT2, BT2P and BT2I (again these bus states are referenced in the cited Intel publications).

BUSCYC386 is high during CPU local bus 230 states TI, Tl, T1P, T2I and low during T2. It is also low for T2P unless T2I occurs first.

CPUNA is a signal to the 80386 processor that allows parallel operation.

LEAB is holding circuit preparation (into buffer 240) for posted writes.

MISSI is active which defines the first period of a double period to handle 64 bit reads to fast storage devices.

PIPECYC385 is active during BT1P (which is a bus state referred to in the cited Intel publications).

PIPECYC386 is low during the T1P state of the CPU local bus 230.

CPUREADY is the ready input to the 80386 processor.

The NCA is a signal formed by decoding the address component on the CPU local bus 230 to reflect, when active, a non-storable access. The cacheability is determined by a tag component (A31 through A17) and programmable information that defines which tags (if any) refer to cacheable as opposed to non-cacheable addresses.

NACACHE is a signal similar to the BNA signal. BNA is a system-generated signal that requests the next address from the CPU local bus 230 and is referenced in the cited Intel publications. NACACHE differs from BNA only with regard to . to the fact that BNA is formed for 32K cache while NACACHE is formed for a 64K cache. As long as the cache is 32K, as mentioned in the Intel publications, the NACACHE signal referred to here could be replaced by the BNA signal.

READY0387 is the ready output signal of the 80387 math coprocessor.

The RDY387PAL is an output to external logic used in the event that an 80387 math coprocessor is not installed to prevent the absence of the math coprocessor from interfering with system operations.

It should be noted that when using the present invention with a dual bus microcomputer system using an 80386 processor and an 82385 RAM controller, the processor is conditionally allowed to PREEMPTE for use of the system bus under certain conditions. Specifically, for local bus periods that extend over a predetermined duration, the processor may assert /CPREEMPT provided that there are other users requesting access to the source and the PREEMPT option has been made ready (ENC-PUPREEMPT). However, when the PREEMPT becomes effective (as signaled to the processor by the arbitrary monitor) the two cases occur simultaneously. The first case is that the processor accesses the system bus. This access will not interfere with other potential bus users since other requesting users are in the arbitrary phase during the processor's access period. Simultaneously with the access to the system bus by the processor, other users can thus arbitrarily access the access phase that follows the processor's use of the bus. When using the invention, the processor is thus prepared for use of the system bus even if other devices request access to the bus at the same time. By overlapping the processor's use of the bus with the arbi tree phase (entered by other devices), bus usage and efficiency are increased.

Claims (6)

1. Multi-bus microcomputer system including a processor (225) and a flash storage subsystem (260) connected together by a CPU local bus (230), a direct storage (255), a system bus (250) and several other functional units (275, 280, 285, 290, 295, 300, 305, 310, 315) connected together by means of the system bus (250), and devices (240) which connect the CPU local bus (230) and the system bus (250), characterized in that the system bus (250) includes several conductors dedicated to arbitration access to the system bus (250 ) by means of at least some of the other functional units, wherein one of the conductors carries a PREEMPT signal to any functional unit with access to the system bus to limit the duration of the access in response to receipt of the PREEMPT signal, and that a PREEMPT signal source (501, 502, 503) having inputs responsive to a CPU local bus cycle extending beyond a minimum duration to assert a PREEMPT signal on the system bus (250). 2. The multi-bus microcomputer system of claim 1, characterized by an arbitration monitor (335) including a source of an arbitrary grant signal (ARB/GRANT), means responsive to the PREEMPT signal to prepare for an arbitration phase, means for initiating an arbitration phase in response to a signal representing the termination of a running bus user's use of the bus, and means (HRQ) for signaling a new arbitration phase to the processor. 3. Multi-bus microcomputer system according to claim 2, characterized in that the processor responds to signaling (HRQ) from the arbitrary monitor (335) representing a new arbitrary ase while the PREEMPT signal is asserted to immediately access the system bus (250). 4. Multi-bus microcomputer system according to any one of the preceding claims, characterized in that the PREEMPT signal source (501, 502, 503) is further responsive to a programmable signal (ENCPUPREEMPT) to allow generation of the PREEMPT signal in a state of the programmable signal and to inhibit generation of the PREEMPT signal when the programmable signal is in a further state. 5. Multi-bus microcomputer system according to one of the preceding claims, characterized by a selection bus (320) coupled with the system bus (250) and the device for coupling to the CPU local bus (230), whereby the device coupled with the selection bus can arbitrarily from access to the system bus and is responsive to PREEMPT signal from the PREEMPT signal source to terminate a bus access in response to receiving the PREEMPT signal. 6. Multi-bus microcomputer system according to claim 1, characterized in that several conductors include an arbitrary permission conductor carrying an arbitrary permission signal to establish an arbitrary phase for arbitrating access among several devices when the signal is in a state and a permission phase for use of the system bus by the device receiving the arbitrary phase , and that the CPU includes a device for accessing the system bus in the arbitrary phase immediately followed by the PREEMPT signal.