JPH0172733U - - Google Patents
Info
- Publication number
- JPH0172733U JPH0172733U JP1987169371U JP16937187U JPH0172733U JP H0172733 U JPH0172733 U JP H0172733U JP 1987169371 U JP1987169371 U JP 1987169371U JP 16937187 U JP16937187 U JP 16937187U JP H0172733 U JPH0172733 U JP H0172733U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- gate
- counts
- input
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001186 cumulative effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
- Manufacturing Of Magnetic Record Carriers (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は第１図に示すパルスカウンタ装置のタイ
ムチヤートである。
１，２……プリセツトカウンタ、３，５……イ
ンバータ、４，６，７……ＡＮＤゲート、８，９
……トータルカウンタ、ａ……位置データ信号、
ｂ……位置データ信号、ｃ……位置パルス入力信
号、ｉ……パルス入力信号。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a time chart of the pulse counter device shown in FIG. 1. 1, 2...Preset counter, 3, 5...Inverter, 4, 6, 7...AND gate, 8, 9
...Total counter, a...Position data signal,
b...Position data signal, c...Position pulse input signal, i...Pulse input signal.
Claims (1)
、その累積が第１の位置データ信号に設定された
値に達するとハイレベル信号を出力する第１のプ
リセツトカウンタと、前記第１のパルス信号が入
力される毎にカウントしその累積数が第２の位置
データ信号に設定された値に達するとハイレベル
信号を出力する第２のプリセツトカウンタと、第
１のプリセツトカウンタからの出力信号と第２の
プリセツトカウンタからの出力信号とが接続され
た第１のＡＮＤゲートと、前記第１のＡＮＤゲー
トからの出力信号の反転信号と第２のパルス信号
が入力される第２のＡＮＤゲートと、前記第１の
ＡＮＤゲートからの出力信号と前記第２のパルス
信号が入力される第３のＡＮＤゲートと、前記第
２のＡＮＤゲートからの出力信号中のパルス数を
カウントする第１のトータルカウンタと、前記第
３のＡＮＤゲートからの出力信号中のパルス数を
カウントする第２のトータルカウンタとを含むこ
とを特徴とするパルスカウント装置。 a first preset counter that counts each time a first pulse signal is input and outputs a high level signal when the cumulative count reaches a value set in the first position data signal; A second preset counter that counts each time a signal is input and outputs a high level signal when the cumulative number reaches the value set in the second position data signal, and an output from the first preset counter. a first AND gate to which the signal and the output signal from the second preset counter are connected; and a second AND gate to which the inverted signal of the output signal from the first AND gate and a second pulse signal are input. an AND gate, a third AND gate into which the output signal from the first AND gate and the second pulse signal are input, and a third AND gate that counts the number of pulses in the output signal from the second AND gate. 1. A pulse counting device comprising: a total counter; and a second total counter that counts the number of pulses in an output signal from the third AND gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987169371U JPH0172733U (en) | 1987-11-04 | 1987-11-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987169371U JPH0172733U (en) | 1987-11-04 | 1987-11-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0172733U true JPH0172733U (en) | 1989-05-16 |
Family
ID=31459367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987169371U Pending JPH0172733U (en) | 1987-11-04 | 1987-11-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0172733U (en) |
-
1987
- 1987-11-04 JP JP1987169371U patent/JPH0172733U/ja active Pending