JPH0172734U - - Google Patents
Info
- Publication number
- JPH0172734U JPH0172734U JP1987169372U JP16937287U JPH0172734U JP H0172734 U JPH0172734 U JP H0172734U JP 1987169372 U JP1987169372 U JP 1987169372U JP 16937287 U JP16937287 U JP 16937287U JP H0172734 U JPH0172734 U JP H0172734U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- event
- count
- outputs
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Manufacturing Of Magnetic Record Carriers (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図ａ〜ｅは本考案のカウント装置の動作を示
すタイミングチヤートである。
１……ＲＳフリツプフロツプ、２……ＡＮＤゲ
ート、３……トータルカウンタ、４……プリセツ
トカウンタ、ａ……インデツクスパルス、ｂ……
イベントパルス、ｃ……イベント信号、ｄ……カ
ウントアツプ信号、ｅ……イベントゲート信号、
ｆ……イベントデータ、ｇ……インデツクスデー
タ、ｈ……リセツト信号。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIGS. 2a to 2e are timing charts showing the operation of the counting device of the present invention. 1...RS flip-flop, 2...AND gate, 3...total counter, 4...preset counter, a...index pulse, b...
Event pulse, c...event signal, d...count up signal, e...event gate signal,
f...Event data, g...Index data, h...Reset signal.
Claims (1)
号を出力し、インデツクスパルスで前記イベント
信号がローレベルになるＲＳフリツプフロツプと
、インデツクスデータがセツトされ前記インデツ
クスパルスをカウントし前記インデツクスデータ
にカウント値がなつたときローレベルになるカウ
ントアツプ信号を出力しリセツト信号で前記カウ
ントアツプ信号がハイレベルになるプリセツトカ
ウンタと、前記カウントアツプ信号がハイレベル
の間、前記イベント信号をイベントゲート信号と
して出力するＡＮＤゲートと、前記イベントゲー
ト信号をカウントしカウント値として、イベント
データを出力し前記リセツト信号でカウント値が
リセツトされるトータルカウンタとを含むことを
特徴とするカウント装置。 An RS flip-flop that outputs an event signal that goes high with an event pulse and goes low with an index pulse, and an RS flip-flop that sets the index data, counts the index pulse, and stores the count value in the index data. a preset counter that outputs a count-up signal that becomes low level when the count-up signal reaches a low level, and the count-up signal becomes high level with a reset signal, and outputs the event signal as an event gate signal while the count-up signal is high level. A counting device comprising an AND gate and a total counter that counts the event gate signal, outputs event data as a count value, and whose count value is reset by the reset signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987169372U JPH0172734U (en) | 1987-11-04 | 1987-11-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987169372U JPH0172734U (en) | 1987-11-04 | 1987-11-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0172734U true JPH0172734U (en) | 1989-05-16 |
Family
ID=31459369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987169372U Pending JPH0172734U (en) | 1987-11-04 | 1987-11-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0172734U (en) |
-
1987
- 1987-11-04 JP JP1987169372U patent/JPH0172734U/ja active Pending
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