JPS6037932U - pulse generator - Google Patents
pulse generatorInfo
- Publication number
- JPS6037932U JPS6037932U JP1983130224U JP13022483U JPS6037932U JP S6037932 U JPS6037932 U JP S6037932U JP 1983130224 U JP1983130224 U JP 1983130224U JP 13022483 U JP13022483 U JP 13022483U JP S6037932 U JPS6037932 U JP S6037932U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- counter
- pulse width
- output
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係るパルスジェネレータの一実施例を
示すブロック図、第２図及び第３図は夫々第１図の回路
の動作を説明する為の波形図である。
１０・・・・・・プロセッサ、２０・・・・・・基準ク
ロック、３０・・・・・・パルス幅カウンタ、４０・曲
・パルス数カウンタ、５０・・・・・・パルス数カウン
タ、６ｏ・・・・・・オ ′アゲート、７０・・
・・・・ツブ、ＢＵＳＹ用フリップ・フロップ。FIG. 1 is a block diagram showing one embodiment of a pulse generator according to the present invention, and FIGS. 2 and 3 are waveform diagrams for explaining the operation of the circuit shown in FIG. 1, respectively. 10...Processor, 20...Reference clock, 30...Pulse width counter, 40 Music/Pulse number counter, 50...Pulse number counter, 6o・・・・・・O 'Agate, 70...
... Flip-flop for BUSY.
Claims (1)
た値に応じた周期のパルスを出力するパルス周期カウン
タ、このパルス周期カウンタの出力によりトリガされ前
記基準クロックを分周して。 指定された値に応じたパルス幅信号を出力するパルス幅
カウンタ、及びこのパルス幅カウンタの出力パルス数を
計数し計数値が指定された値に一致すると出力パルスを
発生すると共に前記パルス周期カウンタとパルス幅カウ
ンタをリセットするリセット信号を出力するパルス数カ
ウンタを内蔵してなるパルスジェネレータ。[Claims for Utility Model Registration] A reference clock, a pulse period counter that divides this reference clock and outputs a pulse with a period according to a specified value, and is triggered by the output of this pulse period counter to output the reference clock. Divide the frequency. A pulse width counter that outputs a pulse width signal according to a specified value, and a pulse width counter that counts the number of output pulses of this pulse width counter and generates an output pulse when the counted value matches the specified value. A pulse generator with a built-in pulse number counter that outputs a reset signal to reset the pulse width counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983130224U JPS6037932U (en) | 1983-08-23 | 1983-08-23 | pulse generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983130224U JPS6037932U (en) | 1983-08-23 | 1983-08-23 | pulse generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6037932U true JPS6037932U (en) | 1985-03-15 |
Family
ID=30294806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983130224U Pending JPS6037932U (en) | 1983-08-23 | 1983-08-23 | pulse generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6037932U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0292014A (en) * | 1988-09-28 | 1990-03-30 | Nec Corp | Signal output circuit |
-
1983
- 1983-08-23 JP JP1983130224U patent/JPS6037932U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0292014A (en) * | 1988-09-28 | 1990-03-30 | Nec Corp | Signal output circuit |
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