JPS5945666U - Noise removal circuit - Google Patents
Noise removal circuitInfo
- Publication number
- JPS5945666U JPS5945666U JP14225582U JP14225582U JPS5945666U JP S5945666 U JPS5945666 U JP S5945666U JP 14225582 U JP14225582 U JP 14225582U JP 14225582 U JP14225582 U JP 14225582U JP S5945666 U JPS5945666 U JP S5945666U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input signal
- outputs
- noise removal
- reference signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、雑音除去回路の回路図、第２図は、第１図の
回路の各部の波形図である。
ＣＧ・・・基準信号発生回路、Ｆｌ、 Ｆ２・・・第１
、第２のエツジトリガーフリップフロップ、Ａ・・・Ａ
ＮＤ回路。FIG. 1 is a circuit diagram of a noise removal circuit, and FIG. 2 is a waveform diagram of each part of the circuit of FIG. CG...Reference signal generation circuit, Fl, F2...1st
, second edge-trigger flip-flop, A...A
ND circuit.
Claims (1)
さい周期を有する基準信号を発生する基準信号発生回路
と、 □ 入力信号を上記基準信号の立上りで監視し、その立
上り時における入力信号の状態を保持し、出力する第１
の回路と、 入力信号を上記基準信号の立下り監視し、その立下り時
における入力信号の状態を保持し、出力する第２の回路
と、 上記第１および第２の回路の岡山力信号の論理積信号を
出力するＡＮＤ回路と、− を有する雑音′除去回路。[Claims for Utility Model Registration] A reference signal generation circuit that generates a reference signal having a period smaller than the minimum pulse width and minimum pulse interval of an input signal; □ Monitoring the input signal with the rise of the reference signal; The first one that holds and outputs the state of the input signal at the time.
a second circuit that monitors the input signal at the falling edge of the reference signal, holds and outputs the state of the input signal at the time of the falling edge, and a second circuit that monitors the falling edge of the reference signal and outputs the input signal; An AND circuit that outputs an AND signal, and a noise removal circuit that has -.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14225582U JPS5945666U (en) | 1982-09-20 | 1982-09-20 | Noise removal circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14225582U JPS5945666U (en) | 1982-09-20 | 1982-09-20 | Noise removal circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5945666U true JPS5945666U (en) | 1984-03-26 |
Family
ID=30317917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14225582U Pending JPS5945666U (en) | 1982-09-20 | 1982-09-20 | Noise removal circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5945666U (en) |
-
1982
- 1982-09-20 JP JP14225582U patent/JPS5945666U/en active Pending
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