JPS59151174U - signal processing device - Google Patents
signal processing deviceInfo
- Publication number
- JPS59151174U JPS59151174U JP2150184U JP2150184U JPS59151174U JP S59151174 U JPS59151174 U JP S59151174U JP 2150184 U JP2150184 U JP 2150184U JP 2150184 U JP2150184 U JP 2150184U JP S59151174 U JPS59151174 U JP S59151174U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- flip
- receives
- processing device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Radar Systems Or Details Thereof (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の一実施例による信号処理装置を示す
ブロック図、第２図から第６図までは第１図に示した各
ブロックの動作波形図である。
なお図中同一符号は同−又は相当部分を示す。
３・・・第１のシュミット回路、４・・・第２のシュミ
ット回路、６・・・第１のフリップフロップ回路、７・
・・第２のフリップフロップ回路、８・・・第３のフリ
ッ、プフロツプ回路、１０・・・保持回路、１４・・・
フィルタ回路。FIG. 1 is a block diagram showing a signal processing device according to an embodiment of this invention, and FIGS. 2 to 6 are operation waveform diagrams of each block shown in FIG. 1. Note that the same reference numerals in the figures indicate the same or equivalent parts. 3... First Schmitt circuit, 4... Second Schmitt circuit, 6... First flip-flop circuit, 7...
...Second flip-flop circuit, 8...Third flip-flop circuit, 10...Holding circuit, 14...
filter circuit.
Claims (1)
１のシュミット回路、上記入力信号の基準電位に対して
負の閾値電圧で動作する第２のシュミット回路、上記第
１のシュミット回路の出力信号と一定の周期を有するパ
ルス信号を入力とする第１のフリップフロップ回路、上
記第２のシュミット回路の出力信号と上記パルス信号を
入力とする第２のフリップフロップ回路、上記第１及び
第２のフリップフロップ回路のそれぞれの出力信号を入
力とする第３のフリップフロップ回路、この第３のフリ
ップフロップ回路の出力信号を入力とじ上記パルス信号
の周期より短い時間上記第３のフリップフロップ回路の
出力信号に応じた信号を保持する保持回路、この保持回
路の出力信号に応じた低周波信号を取り出すフィルタ回
路を備えたことを特徴とする信号処理装置。a first Schmitt circuit that operates with a positive threshold voltage with respect to the reference potential of the input signal; a second Schmitt circuit that operates with a negative threshold voltage with respect to the reference potential of the input signal; a first flip-flop circuit that receives an output signal and a pulse signal having a constant period; a second flip-flop circuit that receives an output signal of the second Schmitt circuit and the pulse signal; a third flip-flop circuit that receives the output signals of the second flip-flop circuit; A signal processing device comprising: a holding circuit that holds a signal corresponding to an output signal; and a filter circuit that extracts a low frequency signal corresponding to the output signal of the holding circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2150184U JPS59151174U (en) | 1984-02-16 | 1984-02-16 | signal processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2150184U JPS59151174U (en) | 1984-02-16 | 1984-02-16 | signal processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59151174U true JPS59151174U (en) | 1984-10-09 |
| JPS6331021Y2 JPS6331021Y2 (en) | 1988-08-18 |
Family
ID=30152624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2150184U Granted JPS59151174U (en) | 1984-02-16 | 1984-02-16 | signal processing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59151174U (en) |
-
1984
- 1984-02-16 JP JP2150184U patent/JPS59151174U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6331021Y2 (en) | 1988-08-18 |
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