JPS5937642U - Standby signal generator - Google Patents

Standby signal generator

Info

Publication number
JPS5937642U
JPS5937642U JP13257582U JP13257582U JPS5937642U JP S5937642 U JPS5937642 U JP S5937642U JP 13257582 U JP13257582 U JP 13257582U JP 13257582 U JP13257582 U JP 13257582U JP S5937642 U JPS5937642 U JP S5937642U
Authority
JP
Japan
Prior art keywords
standby signal
input terminal
supplied
signal generator
positive voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13257582U
Other languages
Japanese (ja)
Inventor
春樹 石持
山村 喜美夫
裕二 福山
柳井 正人
智 高橋
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP13257582U priority Critical patent/JPS5937642U/en
Publication of JPS5937642U publication Critical patent/JPS5937642U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の待機信号発生装置のブロック線図、第2
図は同従来装置における入出力信号波形図、第3図は本
考案の1実施例のブロック線図、第4図は同実施例にお
ける入出力信号波形図である。 4・・・JK型ラフリップフロップ
Figure 1 is a block diagram of a conventional standby signal generator, Figure 2 is a block diagram of a conventional standby signal generator;
3 is a block diagram of an embodiment of the present invention, and FIG. 4 is an input/output signal waveform diagram of the same embodiment. 4...JK type rough flip-flop

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] JK型ラフリップフロップJ、に入力端子及びプリセッ
ト入力端子には正電圧を印加し、クロック入力端子にク
ロックパルスを供給し、クリア入力端子にはメモリ読出
し信号を供給し、Q若しくはQ出力端子より待機信号を
取出すようにしたことを特徴とする待機信号発生装置。
A positive voltage is applied to the input terminal and preset input terminal of the JK type rough flip-flop J, a clock pulse is supplied to the clock input terminal, a memory read signal is supplied to the clear input terminal, and the Q or Q output terminal is supplied with a positive voltage. A standby signal generating device characterized in that it extracts a standby signal.
JP13257582U 1982-08-31 1982-08-31 Standby signal generator Pending JPS5937642U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13257582U JPS5937642U (en) 1982-08-31 1982-08-31 Standby signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13257582U JPS5937642U (en) 1982-08-31 1982-08-31 Standby signal generator

Publications (1)

Publication Number Publication Date
JPS5937642U true JPS5937642U (en) 1984-03-09

Family

ID=30299342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13257582U Pending JPS5937642U (en) 1982-08-31 1982-08-31 Standby signal generator

Country Status (1)

Country Link
JP (1) JPS5937642U (en)

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