JPS59164335U - pulse generator - Google Patents
pulse generatorInfo
- Publication number
- JPS59164335U JPS59164335U JP5821883U JP5821883U JPS59164335U JP S59164335 U JPS59164335 U JP S59164335U JP 5821883 U JP5821883 U JP 5821883U JP 5821883 U JP5821883 U JP 5821883U JP S59164335 U JPS59164335 U JP S59164335U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- data
- pulse generator
- memory
- carry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の一実施例によるパルス発生器の回路
図、第２図及び第３図は第１図に示す回路から出力され
るパルス列の波形図である。
１・・・マイクロプロセッサ、２・・・メモリ、３・・
・コントロールロジック、４・・・発振器、５・・・カ
ウンタ、６・・・フリップフロップ、７・・・バッファ
である。FIG. 1 is a circuit diagram of a pulse generator according to an embodiment of the invention, and FIGS. 2 and 3 are waveform diagrams of a pulse train output from the circuit shown in FIG. 1. 1...Microprocessor, 2...Memory, 3...
- Control logic, 4... Oscillator, 5... Counter, 6... Flip-flop, 7... Buffer.
Claims (1)
を記憶したメモリと、上記メモリより読み出したデータ
をプリセットした後、キャリを発生するまでクロックを
カウントするカウンタと、上記カウンタのキャリにより
反転され、上記パルス列を出力するフリップフロップと
、上記カウンタのキャリにより上記データに読く他のデ
ータを読み出すためのアドレス及び読み出し信号を供給
するコントロールロジックとを備えたパルス発生装置。a memory that stores data for specifying the pulse width of a pulse train to be generated; a counter that counts clocks until a carry is generated after presetting the data read from the memory; and a counter that is inverted by the carry of the counter; A pulse generator comprising: a flip-flop that outputs the pulse train; and a control logic that supplies an address and a read signal for reading other data to the data by carrying the counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5821883U JPS59164335U (en) | 1983-04-18 | 1983-04-18 | pulse generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5821883U JPS59164335U (en) | 1983-04-18 | 1983-04-18 | pulse generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59164335U true JPS59164335U (en) | 1984-11-05 |
Family
ID=30188500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5821883U Pending JPS59164335U (en) | 1983-04-18 | 1983-04-18 | pulse generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59164335U (en) |
-
1983
- 1983-04-18 JP JP5821883U patent/JPS59164335U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59164335U (en) | pulse generator | |
| JPS59164334U (en) | pulse generator | |
| JPS5999298U (en) | Dynamic memory access timing circuit | |
| JPS5937642U (en) | Standby signal generator | |
| JPS6074336U (en) | pulse generator | |
| JPS5847945U (en) | Request signal processing circuit | |
| JPS60164258U (en) | data transfer control device | |
| JPS58129770U (en) | Billing pulse generator | |
| JPS5986742U (en) | Programmable timing generation circuit | |
| JPS60176481U (en) | display control device | |
| JPS5872798U (en) | PROM writing confirmation device | |
| JPS5978595U (en) | Memory stop circuit | |
| JPS59100306U (en) | Sequence control calculation device | |
| JPS6080600U (en) | Electrically erasable PROM | |
| JPS5927638U (en) | Frequency divider circuit | |
| JPS6117891U (en) | Inverter control device | |
| JPS58109898U (en) | P-ROM writer | |
| JPS60119138U (en) | Pulse generation circuit | |
| JPS58107633U (en) | Output circuit | |
| JPS60192039U (en) | data storage device | |
| JPS60184134U (en) | memory backup device | |
| JPS59153596U (en) | Storage device | |
| JPS601037U (en) | binary circuit | |
| JPS603999U (en) | LSI with built-in memory | |
| JPS58118600U (en) | Pulse generation circuit |