JPS58132433U

JPS58132433U - buffer circuit

Info

Publication number: JPS58132433U
Application number: JP2891482U
Authority: JP
Inventors: 川合　孝裕; 岩滝　雅人
Original assignee: 株式会社日立製作所
Priority date: 1982-03-03
Filing date: 1982-03-03
Publication date: 1983-09-07

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案の原理的回路図、第２図は第１図のタイ
ミングチャートである。１・・・・・・カウンター、２・・・・・・専用論理回
路、３・・・・・・カウンター、４・・・・・・カウン
ター、５・・・・・・専用論理回路。FIG. 1 is a principle circuit diagram of the present invention, and FIG. 2 is a timing chart of FIG. 1. 1... Counter, 2... Dedicated logic circuit, 3... Counter, 4... Counter, 5... Dedicated logic circuit.

Claims

[Scope of utility model registration request]

In a buffer circuit including a monostable multivibrator that detects a change in an input signal and outputs a pulse of a constant width in accordance with the change, a first
a second counter that counts the final output of the buffer circuit; a logic circuit that outputs a signal only when the outputs of the first and second counters meet certain conditions; There is a third counter that can start counting and reset the constant frequency pulse that is input separately by the output of the counter, and the output of the third counter outputs a pulse of a constant width as the final output of this circuit when a certain condition is met. A buffer circuit comprising a dedicated logic circuit including an output monostable multivibrator.