JPS5811338U - Frequency divider circuit - Google Patents
Frequency divider circuitInfo
- Publication number
- JPS5811338U JPS5811338U JP10438281U JP10438281U JPS5811338U JP S5811338 U JPS5811338 U JP S5811338U JP 10438281 U JP10438281 U JP 10438281U JP 10438281 U JP10438281 U JP 10438281U JP S5811338 U JPS5811338 U JP S5811338U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- detection
- pulse counting
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の分周回路の一例を示すブロック図、第２
図は本考案による分周回路を示すブロック図、第３図は
第２図の回路の主要各点の信号状態を委すタイムチャー
ト、第４図は本考案の一実施例を示す論理構成図、第５
図は第４図の実施例の主要各点の信号状態を示すタイム
チャートである。
１・・・計数回路、２・・・Ｎ−Ｍ検出回路、３・・・
Ｎ検出回路１，４・・・パルス出力回路、５・・・第２
の計数回路、６・・・第１の検出回路、７・・・第２の
検出回路、８・・・第３の検出回路、９・・・論理積回
路、１０・・・パルス反転回路、１１・・・第１の計数
回路。Figure 1 is a block diagram showing an example of a conventional frequency divider circuit;
The figure is a block diagram showing a frequency divider circuit according to the present invention, Figure 3 is a time chart showing signal states at each main point in the circuit of Figure 2, and Figure 4 is a logical configuration diagram showing an embodiment of the present invention. , 5th
The figure is a time chart showing signal states at each main point in the embodiment of FIG. 4. 1... Counting circuit, 2... N-M detection circuit, 3...
N detection circuits 1, 4...pulse output circuit, 5...second
counting circuit, 6... first detection circuit, 7... second detection circuit, 8... third detection circuit, 9... AND circuit, 10... pulse inversion circuit, 11...first counting circuit.
Claims (1)
力パルスの反転信号を計数する第２のパルス計数回路と
、前記第１のパルス計数回路の出力が下記条件の１にな
ったことを検出する第１の検出回路と、前記第２のパル
ス計数回路の出力が、下記条件のｍになったことを検出
する第２の検出回路と、前記第２のパルス計数回路の出
力が下記条件のｎになったことを検出し、この検出出力
により、前記第１と第２のパルス計数回路を初期設定す
る第３の検出回路と、前記第１と第２の検出回路の検出
出力を入力とする論理積回路と、前記論理積回路出力と
第３の検出回路出力によって、その出力が交互に反転さ
せられるパルス出力回路とから成る分周回路。 記 ｎ＞１ ｎ＞ｍ １＝ｍまたはＩ＝ｍ＋１[Claims for Utility Model Registration] A first pulse counting circuit that counts input pulses, a second pulse counting circuit that counts inverted signals of the input pulses, and an output of the first pulse counting circuit under the following conditions. a first detection circuit that detects that the output of the second pulse counting circuit has reached m of the following condition; A third detection circuit detects that the output of the counting circuit reaches n of the following condition, and uses this detection output to initialize the first and second pulse counting circuits; A frequency dividing circuit comprising an AND circuit which receives the detection output of a detection circuit as an input, and a pulse output circuit whose output is alternately inverted by the output of the AND circuit and the output of a third detection circuit. n>1 n>m 1=m or I=m+1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10438281U JPS5811338U (en) | 1981-07-14 | 1981-07-14 | Frequency divider circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10438281U JPS5811338U (en) | 1981-07-14 | 1981-07-14 | Frequency divider circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5811338U true JPS5811338U (en) | 1983-01-25 |
Family
ID=29898982
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10438281U Pending JPS5811338U (en) | 1981-07-14 | 1981-07-14 | Frequency divider circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5811338U (en) |
-
1981
- 1981-07-14 JP JP10438281U patent/JPS5811338U/en active Pending
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