JPS5859257U - pulse transmission device - Google Patents

pulse transmission device

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Publication number
JPS5859257U
JPS5859257U JP15474481U JP15474481U JPS5859257U JP S5859257 U JPS5859257 U JP S5859257U JP 15474481 U JP15474481 U JP 15474481U JP 15474481 U JP15474481 U JP 15474481U JP S5859257 U JPS5859257 U JP S5859257U
Authority
JP
Japan
Prior art keywords
polarity
circuit
pulse width
signal
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15474481U
Other languages
Japanese (ja)
Inventor
修敏 佐藤
Original Assignee
株式会社横河電機製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社横河電機製作所 filed Critical 株式会社横河電機製作所
Priority to JP15474481U priority Critical patent/JPS5859257U/en
Publication of JPS5859257U publication Critical patent/JPS5859257U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来例の動作説明図、第2図は、本考案実施
例の概念的構成図、第3図は、第2図の装置の動作説明
図である。 1・・・送信回路、11・・・パルス幅伸長回路、12
・・・遅延回路、13・・・フリップ・フロップ回路、
14・・・ドライバ、2・・・伝送線路、3・・・受信
回路、  31.32・・・レシーバ、33.34・・
・波形整形回路、35・・・オアゲート。
FIG. 1 is an explanatory diagram of the operation of the conventional example, FIG. 2 is a conceptual block diagram of the embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of the apparatus shown in FIG. 1... Transmission circuit, 11... Pulse width expansion circuit, 12
...Delay circuit, 13...Flip-flop circuit,
14... Driver, 2... Transmission line, 3... Receiving circuit, 31.32... Receiver, 33.34...
・Waveform shaping circuit, 35...OR gate.

Claims (1)

【実用新案登録請求の範囲】 シリアルな2値信号である送信データが与えられこの送
信データのパルス幅を1ビツトのタイムスロットの1倍
以上の時間幅に伸長するパルス幅伸長回路、 シリアルな2値信号である送信データが与えられそれを
分周するフリップ・フロップ回路、前記パルス幅伸長回
路の出力信号と前記フリップΦフロップ回路の互いに逆
な位相の2つの出力信号とが与えられ、パルス幅伸長回
路の出力信号が「1」である期間iこフリップ・フロッ
プ回路の2つの出力信号の論理値の交代にしたがって極
性が交代するバイポーラ信号を生じるドライバ、このド
ライバの出力信号を受信側に伝送する伝送ライン、 この伝送ラインを通じて与えられるバイポーラ信号のそ
れぞれの極性のレベルをそれぞれのスレッシュホルド・
レベルと比較することによって、それぞれの論理値を決
定するレシーバ、および、このレシーバの出力信号を整
形して出力する波形整形回路を具備するパルス伝送装置
において、 前記パルス幅伸長回路の前段または後段に接続される遅
延回路であって、前記レシーバにおいてバイポーラ信号
が一方の極性の「1」から他方の極性の「1」へ変化す
るときの変化開始時点から他方の極性のスレッシュホル
ド・レベルをよぎる時点までの遅れ時間と同信号が「0
」がらどちらかの極性の「1」へ変化するときの変化開
始点からその極性のスレッシュホルド・レベルをよぎる
時点までの遅れ時間との差に等しい遅れ時間を持つ遅延
回路を設けたことを特徴とするパルス伝送装置。
[Claims for Utility Model Registration] A pulse width expansion circuit that is given transmission data that is a serial binary signal and expands the pulse width of the transmission data to a time width that is at least twice as long as a 1-bit time slot. A flip-flop circuit is given transmission data as a value signal and divides it, an output signal of the pulse width expansion circuit and two output signals of mutually opposite phases of the flip Φ-flop circuit are given, and the pulse width is A driver that generates a bipolar signal whose polarity changes according to the alternation of the logical values of the two output signals of the flip-flop circuit for a period i during which the output signal of the expansion circuit is "1", and transmits the output signal of this driver to the receiving side. A transmission line that sets the polarity level of each bipolar signal applied through this transmission line to a respective threshold.
In a pulse transmission device comprising a receiver that determines each logical value by comparing it with a level, and a waveform shaping circuit that shapes and outputs the output signal of this receiver, the pulse width expansion circuit is provided at a stage before or after the pulse width expansion circuit. a delay circuit connected to the receiver, from the time when the bipolar signal starts changing from "1" of one polarity to "1" of the other polarity to the time point when it crosses the threshold level of the other polarity; The delay time until the same signal is “0”
'' to either polarity's ``1'', a delay circuit having a delay time equal to the difference between the change start point and the time when the polarity crosses the threshold level is provided. pulse transmission device.
JP15474481U 1981-10-16 1981-10-16 pulse transmission device Pending JPS5859257U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15474481U JPS5859257U (en) 1981-10-16 1981-10-16 pulse transmission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15474481U JPS5859257U (en) 1981-10-16 1981-10-16 pulse transmission device

Publications (1)

Publication Number Publication Date
JPS5859257U true JPS5859257U (en) 1983-04-21

Family

ID=29947337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15474481U Pending JPS5859257U (en) 1981-10-16 1981-10-16 pulse transmission device

Country Status (1)

Country Link
JP (1) JPS5859257U (en)

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