SU1372604A1 - Pulse generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for discrete information processing. The purpose of the invention is to expand the range of adjustment of the duty cycle of the output pulses - achieved by introducing a fourth NAND element and a second delay element into the pulse generator. FIG. 1 shows the AND-HE elements 1, 2, 3, and 4, the capacitor 5, the delay elements 6 and 7, the input bus 8, the output bus 9. The operation of the device is illustrated by the timing diagrams provided in the description of the invention. On the output bus 9, pulses are received, the oscillation period of which is determined by the sum of the recharging time of the capacitor 5, where t s is the delay time on elements 6 and 7, respectively. The durability of the output pulses depends on the ratio of delays and tjg t. The range of adjustment of the duty ratio extends from the high frequency region to the low frequency region and can reach high values of the duty cycle. 2 or .. with (L

Description

with y

05

Fm.1

The invention relates to a pulse technique and can be used in discrete information processing devices.

The purpose of the invention is to expand the range of adjustment of the duty cycle of the output pulses.

FIG. 1 shows the functional scheme of the device; in fig. 2 - time diagrams that show his work.

The generator contains the elements AND-NOT 1-4, the capacitor 5, the elements 6 and 7 of the delay, the input 8 and the output 9 bus, the first input of the element AND-NOT 1 is connected to the first plate of the capacitor 5, the second plate of which is connected to the output element AND-NOT 1 and the input element AND-NOT 2, the output of the element AND-NO 3 through the first delay element 6 is connected to the second input of the element AND-NOT 1, the input of the second delay element 7 is connected to the output of the element AND-NOT 2, and the output is with the first inputs of the elements AND-HE 3 and 4, the second input of the element AND-NO 4 is connected to the input bus 8, and the second input is AND-coagulant third output of AND-NO element 1, an output of AND-Nyo 3 is connected to the output line 9, an output of AND-NO element 4 is connected to a first input of AND-NO 1.

The generator works as follows.

When a zero potential acts on bus 8 (FIG. 2g), then the outputs of the AND-NO elements 4, 2, 3 are the potential of a logical unit, and therefore, the same potential will be at the outputs of the delay elements 6 and 7 (Fig. 2e, e ). At the output of the element, AND-NE 1, the zero potential acts in this case, which determines the initial position of the charged capacitor 5.

When applying the resolving potential Log. On the bus 8, an AND-HE element 4 is triggered and at its output (Fig. 2a) a zero potential is formed after the signal propagation time in this element t., which corresponds to the transition 10 (Fig. 2).

The element AND-NOT 1 begins to close, forming a recharging circuit of capacitor 5. When the output of the element AND-NOT 1 reaches the level of the thresholds U, the elements AND-NO 2, 3 (Fig. 26), the thresholds of which are conditionally taken to be the same (transition 11) The elements AND-NOT 2 and 3 are triggered, which corresponds to transitions 12 and 13, respectively, to the zero state. At time t. ,, equal to the signal delay time in element 7, a zero potential appears at its output (transition 15), and at the output of element 6 (Fig. 2e) a zero potential appears at time tig (transition 14). When the conditions are satisfied, tig 6 th, the output of element 6 acquires a zero level earlier or simultaneously with the output of element 7 (fig.2d). From the drop in potential at the output of element 7, the element AND-NOT 3 (transition 16) and the element AND-NOT 4 (transition 17) go into one state.

The transition 16 causes a delay in the transfer of one:; potential at the output of element 6 and for the duration of transition 18 blocks the operation of the element NAND 1 and the beginning of the recharging of the capacitor 5 to the initial state. Transition 18 causes capacitor 5 to recharge. When the trigger threshold is reached (transition 19), the NAND element 2 changes to a state of one (transition 20), which causes the transition of element 7 to one state (transition 21), in which the AND element - NO 4 goes to the zero state (transition 22).

If the action of the permissive potential on the bus 8 is terminated, then the generator occupies the initial state.

Thus, on bus 9, pulses are received, the oscillation period of which is determined by the sum of the delay t ,, / and t.g and the recharging time of the capacitor 5. The square of the output pulses depends on the ratio of the delays t - and t, gnpH and the conditions t, g L

The range of adjustment of the duty ratio extends from the high-frequency region to the low-frequency region and is limited only by the practical feasibility of delays, and very high duty cycle values can be achieved at t, ttj, i.e. the duty cycle depends not only on t ,, and t.g, but also on the magnitude of the delay t introduced by the capacitor 5.

Claims (1)

Invention Formula A pulse generator containing the first NAND element, the first input of which is connected to the first capacitor plate, the second plate of which is connected to the output of the first NAND element and the input of the second NAND element, the output of the third NAND element is connected to the first delay element the second input of the first NAND element, characterized in that, in order to expand the range of adjustment of the output pulse porosity, the fourth NAND element and the second element are entered into it ki, the input of which is connected to the output of the second NAND element, and the output to the first inputs of the third and fourth NAND elements, the second input of the fourth NAND element is connected to the input bus, and the second input of the third NAND element to the output of the first NAND element, the first input of which is connected to the output of the fourth NAND element. Fi.2