JPS5834458U - Wind pulse forming circuit - Google Patents
Wind pulse forming circuitInfo
- Publication number
- JPS5834458U JPS5834458U JP12817381U JP12817381U JPS5834458U JP S5834458 U JPS5834458 U JP S5834458U JP 12817381 U JP12817381 U JP 12817381U JP 12817381 U JP12817381 U JP 12817381U JP S5834458 U JPS5834458 U JP S5834458U
- Authority
- JP
- Japan
- Prior art keywords
- wind pulse
- monostable multivibrator
- circuit
- pulse forming
- forming circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案を適用できる従来のウィンドパルス形
成回路のブロック図、第２図はこの第１図の構成の動作
説明に用いるタイムチャート、第３図はデータ及びクロ
ック分離回路の一例のブロック図、第４図はこの考案の
一実施例のブロック図、第５図はその一部の構成のブロ
ック図、第６図及び第７図はこの考案の一実施例の動作
説明に用いるタイムチャートである。
１・・・・・・入力端子、２・・・・・・ワンショット
マルチ、３・・・・・・位相比較器、５・・・・・・ｖ
ｃｏ、 ａ・・・・・・データ及びクロック分離回路、
１７・・・・・・パルス幅比較器。Fig. 1 is a block diagram of a conventional wind pulse forming circuit to which this invention can be applied, Fig. 2 is a time chart used to explain the operation of the configuration of Fig. 1, and Fig. 3 is a block diagram of an example of a data and clock separation circuit. 4 is a block diagram of an embodiment of this invention, FIG. 5 is a block diagram of a part of the configuration, and FIGS. 6 and 7 are time charts used to explain the operation of an embodiment of this invention. It is. 1...Input terminal, 2...One shot multi, 3...Phase comparator, 5...V
co, a...data and clock separation circuit,
17...Pulse width comparator.
Claims (1)
ックビットからなるシンク期間が設けられた入力ディジ
タル信号からクロックビットとデータビットとを分離す
るためのウィンドパルスを形成するウィンドパルス形成
回路において、上記シンク期間の上記クロックビットか
らウィンドパルスをＰＬＬ回路により形成すると共に、
このＰＬＬ回路の出力を単安定マルチバイブレータに供
給し、この単安定マルチバイブレータの出力と上記ＰＬ
Ｌ回路で形成されたパルスとから上記単安定マルチバイ
ブレータの遅延時間を補正し、上記データ期間では、こ
の遅延時間が補正された単安定マルチバイブレータを介
された入力ディジタル信号を上記ＰＬＬ回路に供給する
ようにしたウィンドパルス形成回路。In a wind pulse forming circuit for forming a wind pulse for separating a clock bit and a data bit from an input digital signal in which a sync period consisting of a clock bit is provided at the beginning of a data period of a predetermined length that is MFM modulated, the above-mentioned A PLL circuit forms a wind pulse from the clock bit in the sync period, and
The output of this PLL circuit is supplied to a monostable multivibrator, and the output of this monostable multivibrator and the above PL
The delay time of the monostable multivibrator is corrected from the pulses formed by the L circuit, and during the data period, the input digital signal via the monostable multivibrator whose delay time has been corrected is supplied to the PLL circuit. A wind pulse forming circuit designed to do this.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12817381U JPS5834458U (en) | 1981-08-29 | 1981-08-29 | Wind pulse forming circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12817381U JPS5834458U (en) | 1981-08-29 | 1981-08-29 | Wind pulse forming circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5834458U true JPS5834458U (en) | 1983-03-05 |
| JPH0119275Y2 JPH0119275Y2 (en) | 1989-06-05 |
Family
ID=29921878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12817381U Granted JPS5834458U (en) | 1981-08-29 | 1981-08-29 | Wind pulse forming circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5834458U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62177764A (en) * | 1986-01-31 | 1987-08-04 | Oki Electric Ind Co Ltd | Data demodulation circuit |
-
1981
- 1981-08-29 JP JP12817381U patent/JPS5834458U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62177764A (en) * | 1986-01-31 | 1987-08-04 | Oki Electric Ind Co Ltd | Data demodulation circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0119275Y2 (en) | 1989-06-05 |
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