JPH0119275Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention is based on MFM (Modified Frepuency).
(Modulation) A window pulse forming circuit for forming a window pulse for separating clock bits and data bits from a modulated input digital signal.

In MFM modulation, unlike FM modulation, clock bits may not exist, and in order to demodulate it, it is necessary to use a PLL circuit to form a window signal that separates clock bits and data bits. The window signal is, for example, a clock bit when it is "0" and a data bit when it is "1". When the input digital signal is reproduced from a magnetic disk, etc., in order to increase the tolerance for jitter in the reproduced signal, it is necessary to insert a clock bit or data bit at the center of each "0" or "1" section of the wind signal. It is desirable that the

When recording a digital signal by MFM modulation on a magnetic disk, for example, a 32-byte sync period is inserted at the beginning of a 256-byte sector data period. The sync period consists of clock bits. To generate the window signal, the PLL circuit is operated so that the data read from the disk is located at the center of the window signal "0" within this sync period, and after the sync period, the data bit is In this case, feedback is applied so that the data bit is located at the center of "1", and when a clock bit arrives, the clock bit is located at the center of "0". Conventionally, as shown in Fig. 1, a monostable multivibrator 2 (hereinafter referred to as one-shot multi) is triggered by the rising edge of read data RDT from an input terminal 1, and its output pulse is sent to a phase comparator. 3. The comparison output of the phase comparator 3 is passed through an amplifier and a low-pass filter 4.
It is supplied to a VCO (voltage controlled oscillator) 5, and a bit-period window signal WND is taken out at an output terminal 6. During the sync period, the switch circuit 7 supplies the window signal WND to the phase comparator 3 as shown.

FIG. 2A shows a sync period in which the clock bit is repeatedly positioned with a period T, and the pulse shown in FIG. 2B is generated from the one-shot multi 2. Corresponding to the delay time of this one-shot multi 2, the pulse width of its output pulse is t. Second
As shown in Figure C, the wind signal from VCO5
The PLL circuit works so that the rising edge of WND coincides with the falling edge of the one shot multi 2 output.

Further, during the data period, the switch circuit 7 is switched, and the output of the data and clock separation circuit 8 is supplied to the phase comparator 3. As shown in FIG. 3, this data and clock separation circuit 8 is composed of two D-type flip-flops 10 and 11, and read data RDT is supplied as a clock input to both flip-flops.
A window signal WND is supplied as the D input and clear input of one flip-flop 10, and the inverted version thereof is supplied as the D input and clear input of the other flip-flop 11. For example, as shown in FIG. 2D, the read data RDT is
In the case of data (000111...), the data bits shown in FIG. 2E appear from the flip-flop 10, and the clock bits shown in FIG. 2F appear from the flip-flop 11. These two are or gate 1
2 to the phase comparator 3. So in the data period, if a data bit comes,
Compare the falling edge of the one shot multi 2 output (Fig. 2 G) with the falling edge of the wind signal WND, and if a clock bit has arrived, compare the falling edge of the one shot multi 2 output with the rising edge of the wind signal WND. and if neither comes, I try not to compare.

In this conventional configuration, optimal demodulation can be performed by setting the pulse width t of the one-shot multi 2 to 1/2 of the length of "0" or "1" of the wind signal, but due to poor adjustment, temperature changes, If the pulse width t becomes out of order due to aging or the like, there is a risk that the clock bits and data bits will be incorrectly separated, and the demodulated data may be incorrect.

This invention aims to eliminate the above-mentioned problems of the conventional structure, and aims to ensure that the clock bit or data bit is located at the center of the window signal without any adjustment.

One embodiment of this invention will be described below. In FIG. 4 showing the overall configuration of this embodiment, the same reference numerals are given to the constituent parts corresponding to those in FIG. 1. A switch circuit 13 that can be switched between a sync period and a data period is inserted between the input terminal 1 and the input terminal of the one shot multi 2,
A switch circuit 14 is inserted between the output terminal of the one-shot multiplier 2 and the phase comparator 3. In addition, the center frequency of the VCO 5 of the PLL circuit is set to twice the frequency of the wind signal WND, and the 1/2 frequency divider 15 provided at the next stage
WND is allowed to form. This VCO
5 and an inverted version of the window signal WND are supplied to the AND gate 16, and during the sync period, as shown in the figure, the output of the AND gate 16 is supplied to the phase comparator 3 via the switch circuit 7.
It is compared with the read data RDT supplied from the input terminal 1 via the switch circuit 14.

In the sink period, as shown in FIG. 6A, a clock bit with a constant period T is supplied to the input terminal 1 as read data RDT, and the phase is compared with the output of the AND gate 16 shown in FIG. It is controlled so that the rise of the output of the AND gate 16 coincides with the rise. Figure 6C is
D shows a window signal with twice the frequency and pulse width t _r from VCO 5, and D in the same figure shows a window signal from 1/2 frequency divider 15
It shows the wind signal WND appearing from. In this way, the sync period can be defined without adjustment so that the rising edge of the clock bit is located at the center of the "0" period of the window signal.

Further, the one-shot multi 2 is controlled so that its delay time becomes normal within the sync period, and this state is held in the subsequent data period as well. In other words, during the sync period, one shot multi 2 is triggered by the rise of the output of VCO 5, the output of VCO 5 and the output of one shot multi 2 are supplied to pulse width comparator 17, and the difference in the pulse widths of the two is A comparison output of a corresponding level is obtained, and this comparison output is supplied to the one-shot multi 2 as a delay time control signal via the hold circuit 18. The delay time can be controlled by controlling the time constant or power supply voltage of one shot multi 2 using a control signal, or by clearing one shot multi 2 after a predetermined time determined by the control voltage after the output becomes "1". can be controlled. The pulse width comparator 17 has a digital configuration as shown in FIG.

In FIG. 5, the output of the VCO 5 from the terminal 21 and the inverted version of the output of the one-shot multi 2 from the terminal 22 are supplied to the AND gate indicated by 19, and the AND gate indicated by 20 is supplied with the output of the VCO 5 from the terminal 21. The output of the one-shot multi 2 from the terminal 21 and the inverted version of the output of the VCO 5 from the terminal 21 are supplied. Furthermore, this phase comparator 17 is configured to perform a comparison operation only during the sync period, and therefore a timing pulse that becomes "1" is supplied from the terminal 23 only during the sync period. As shown in Figure 7A, VCO5
Let t _r be the pulse width of the output of the one-shot multi 2 as shown in Figure B, and when t _r is larger than t, control the pulse width of (t _r −t). If a signal is available at the output terminal 24 of the AND gate 19 and vice versa, then (t-t _r )
A control signal with a pulse width of is obtained at the output terminal 25 of the AND gate 20, and if (t _r =t), no output of "1" appears at either terminal 24 or 25. By such a comparison, a control signal such as (t _r =t) is generated, and this control is continued by the hold circuit 18 even during the data period.

During the data period, switch circuits 7, 13, 14
is switched from the state shown in the figure, and the output of the one-shot multi 2 and the output from the data and clock separation circuit 8 are compared in the phase comparator 3. The operation during this data period is similar to the conventional configuration shown in Figure 1, but as mentioned above, the delay time (pulse width) of one shot multi 2 is regulated by the detection control of the previous sync period. It is said that

Note that the phase comparison is not limited to the pulse width comparison, and the phase comparison between the output of the one-shot multi-channel 2 and the output of the VCO 5 may be performed.

As understood from the description of one embodiment above,
With this invention, within the sync period, the clock bit can be accurately positioned at the center of the window width, regardless of the one-shot multi delay time.
By using the output of the PLL circuit in this state as a reference, the delay time deviation of the one-shot multi is corrected, and the data bit can be positioned at the center of the window width even in the data period after the sync period. Therefore, the conventional configuration uses read data to trigger a one-shot multiplier that generates a pulse width of half the window width within the sync period, and compares the phase of the output of this one-shot multiplier with the window signal. The difference is that no adjustment is required, and even if there is a shift in the one-shot multi delay time due to poor adjustment, temperature changes, etc., this can be corrected with the clock bit in the sync period, minimizing the effect of jitter. data and clock can be separated correctly.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional wind pulse forming circuit to which this invention can be applied, and Figure 2 is a block diagram of a conventional wind pulse forming circuit to which this invention can be applied.
Figure 3 is a block diagram of an example of a data and clock separation circuit, Figure 4 is a block diagram of an embodiment of this invention, and Figure 5 shows a part of the configuration. Block diagram, No. 6
7 and 7 are time charts used to explain the operation of an embodiment of this invention. 1...Input terminal, 2...One shot multi,
3... Phase comparator, 5... VCO, 8... Data and clock separation circuit, 17... Pulse width comparator.

Claims (1)

[Scope of utility model registration request] In a wind pulse forming circuit that forms a window pulse for separating clock bits and data bits from an input digital signal in which a sync period consisting of a clock bit is provided at the beginning of a data period of a predetermined length that is MFM modulated, the sync period A wind pulse is formed from the above clock bit by a PLL circuit, and this
The output of the PLL circuit is supplied to a monostable multivibrator, and the delay time of the monostable multivibrator is corrected from the output of this monostable multivibrator and the pulse formed by the PLL circuit. A wind pulse forming circuit that supplies an input digital signal via a time-corrected monostable multivibrator to the PLL circuit.