JPS63263920A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To eliminate the uncertainty of the phase condition by adding a flip- flop, an AND circuit and an OR circuit so as to fix the phase difference between an input signal and an output signal to 90 deg., thereby avoiding the stable state with a phase difference of 270 deg.. CONSTITUTION:An input signal (a) is fed to an exclusive OR circuit 1 and a flip-flop (FF) 6, the circuit 1 detects the phase difference between the signal (a) and an output signal (b) and the FF 6 stores the state (high or low level) of the signal (a) at the leading of the signal (b). An output signal (c) of the circuit 1 is converted into a DC signal (d)0 by a low pass filter circuit 2, amplified by an amplifier circuit 3 to control the frequency of an output clock (e) of a voltage controlled oscillator circuit 4. The clock (e) is fed to a frequency division circuit 5 through an AND circuit 8 applying the control of passing or inhibition by the OR between the output signal of the FF 6 being the output signal of an OR circuit 7 and a phase reference signal (f) and generates the signals (b), (f).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a phase synchronized circuit using an exclusive OR circuit as a single phase comparator. The present invention relates to a method and a circuit for solving a problem in which the phase difference between an input signal and an output signal is uncertain as to whether it is 90 degrees or 170 degrees.

2. Description of the Related Art Conventionally, in a phase locked circuit using an exclusive OR circuit as this type of phase comparator, the phase difference between an input signal and an output signal is stabilized at 90 degrees.

There were cases where the body was stable at 0 degrees.

Problems to be Solved by the Invention In the conventional phase-locked circuit described above, the phase difference between the input signal and the output signal is stabilized in some cases at 90 degrees and in other cases at 170 degrees. When a signal is used as a phase reference signal, or when the phase synchronization circuit is used as a timing recovery circuit in data transmission, etc., there is a drawback that the phase condition is uncertain due to the phase relationship between the received signal and decoded data.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel phase-locked circuit which makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, a phase synchronized circuit according to the present invention includes an exclusive OR circuit and a low-pass filter circuit.

It is composed of an amplifier circuit, a voltage controlled oscillator circuit, a frequency divider circuit, a 7-lip 70-tub, an AND circuit, and an OR circuit, and latches the input signal to the flip-flop at the rising or falling edge of the output signal. death.

The logical sum of the output of the flip-flop and the phase reference signal generated by the frequency dividing circuit is used as one input of the AND circuit, and the output signal of the voltage controlled oscillation circuit is added as the other input of the AND circuit. The output of the AND circuit is applied to the frequency dividing circuit to generate an output signal and a phase reference signal, and when the phase difference between the input signal and the output signal is 9θ degrees, the output of the OR circuit is always input as a high level; The phase difference between the outputs is maintained at 90 degrees, and the phase difference between the input signal and the output signal is 2.
In the case of 70 degrees, the output of the flip-flop circuit is set to a low level, and while both the phase reference signals are also at a low level, one input of the AND circuit is set to a low level, and the output signal of the voltage controlled oscillation circuit is set to a low level. It is characterized in that the phase of the output signal is changed by prohibiting the signal from passing through the input signal and the output signal becomes stable when the phase difference between the input signal and the output signal becomes 9θ degrees.

Embodiments Next, seven preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

8g1 In Figure 2, the input signal a is applied to the exclusive OR circuit l and the flip-flop B, and the exclusive OR circuit l detects the phase difference with the output signal A.

In the flip-flop 6, the state of the input signal a (either high level or low level) is determined by the rise of the output signal S.
is memorized. The output signal C of the exclusive OR circuit 1 is applied to a low-pass filter circuit 1 and converted into a DC voltage d.

The DC voltage d is amplified by an amplifier circuit 3 and controls the frequency of the output clock e of the voltage controlled oscillation circuit μ. The clock e passes through an AND circuit g and is then passed through a frequency dividing circuit! is added to the output signal f to generate a phase reference signal f. However, in the AND circuit g.

Control is performed as to whether the clock e is passed or prohibited by the logical sum of the output signal of the flip-flop base, which is the output signal of the OR circuit, and the phase reference signal.

FIG. 1 is a circuit diagram showing an embodiment of the low-pass filter circuit used in the present invention, and switches II and /U are controlled by a signal C to be 1 on and 1 off.

When the signal C is at a high level, the switch l/ is controlled so that it is 1 on and the switch /2 is 1 off, and when the signal C is at a low level, the switch l/ is 1 off and the switch /U is 1 on. be done.

Next, the operation of FIG. 1 will be explained. When the switch l/ is 1 "on" and the switch /:1 is 1 off, the current 1 generated in the constant current circuit 9 flows through the resistor 13. It flows to the ground through the capacitor/da, and the DC voltage d becomes positive. On the other hand, switch // is 1 off.

When the switch /:t is 1 on, current 1 flows from the ground through the capacitor and resistor /J to the constant current circuit 10, and the DC voltage d becomes negative.

Therefore, when controlling switches // and /1 with signal C,
A DC voltage d corresponding to the 0 time ratio between the high level state and the low level state of the signal C is obtained. By the way, the time ratio is l to l.
In this case, the DC voltage d becomes zero volts.

Figures 3 (C) and (C) are time charts for explaining the operation of the block diagram in Figure 1. Figure 3 (C) shows the case where the phase difference between the input signal and the output signal is 9θ degrees, The phase reference signal f becomes low level for a time width corresponding to one period of the clock e at a point l/λ of the time width in which the output signal is in a high level state and is in a high level state on the one time axis. It is set as follows.

To explain the operation with reference to Figure 3 (C) and Figure 1, the output of the flip-flop B is fixed at a high level, so the output of the OR circuit is always at a high level, and the clock e is , the phase difference between the input signal a and the output signal S continues to be maintained at 11 of 90 degrees.

Next, in the case of the phase relationship shown in FIG. 3(C), the output of the flip-flop B becomes a low level, and the output of the OR circuit becomes a low level only when the phase reference signal is at a low level. Therefore, the clock e is set by the AND circuit g/
Only the period is prohibited and added to the frequency division g85. As a result, the phases of the output signals S and F are shifted by one period of the clock e.

When the phase of the output signal S is shifted, a difference occurs in the time width between the high level and the low level of the signal C, and the DC voltage d deviates from zero volts, changing the frequency of the clock e. The phase relationship between input signal a and output signal S is shown in Figure 3 (
When the phase of the output signal S changes until it reaches the relationship shown in Figure 3 (C), a stable state is reached, and the phase relationship shown in Figure 3 (C) continues to be maintained.

As described in detail, according to the present invention, a flip-flop, an AND circuit, and an OR circuit are only added to the conventional phase-locked circuit that uses an exclusive OR circuit as a phase comparator, and the input signal is The phase difference between the output signal and the output signal can be fixed at 90 degrees, and the effect of eliminating the uncertainty of whether it is 90 degrees or 270 degrees, which is seen in conventional circuits, can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 1 is a circuit diagram showing an embodiment of a low-pass filter circuit, and Figs. 3 (C) and (C) explain the operation of Fig. 1. This is a quick time chart.

Claims (1)

[Claims] In a phase-locked circuit having an exclusive OR circuit, a low-pass filter circuit, an amplifier circuit, a voltage-controlled oscillator circuit, a frequency divider circuit, a flip-flop, an AND circuit, and an OR circuit, the input signal is input at the rising or falling edge of the output signal. The output of the flip-flop is latched, and the logical sum of the output of the flip-flop and the phase reference signal generated by the frequency dividing circuit is used as one input of the AND circuit, and the other input of the AND circuit is the voltage controlled oscillation signal. The output signal of the circuit is added, and the output of the AND circuit is added to the frequency divider circuit to generate an output signal and a phase reference signal, and when the phase difference between the input signal and the output signal is 90 degrees, the OR circuit always The output is set to high level and the phase difference between the input and output is maintained at 90 degrees, and when the phase difference between the input signal and the output signal is 270 degrees, the output of the flip-flop circuit is set to low level, and the phase reference signal is also set to While it is at a low level, one input of the AND circuit is set at a low level to prohibit the output signal of the voltage controlled oscillation circuit from passing through the AND circuit, thereby changing the phase of the output signal. A phase synchronized circuit characterized by being stable when the phase difference becomes 90 degrees.