JPS5915235B2 - phase synchronizer - Google Patents
phase synchronizerInfo
- Publication number
- JPS5915235B2 JPS5915235B2 JP4975079A JP4975079A JPS5915235B2 JP S5915235 B2 JPS5915235 B2 JP S5915235B2 JP 4975079 A JP4975079 A JP 4975079A JP 4975079 A JP4975079 A JP 4975079A JP S5915235 B2 JPS5915235 B2 JP S5915235B2
- Authority
- JP
- Japan
- Prior art keywords
- phase
- range
- frequency
- signal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
- H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
Description
【発明の詳細な説明】
本発明は例えば入力信号としてテレビジョン信号の入力
水平同期信号の位相が１ライン又は数ライン変化した場
合、高速で位相ロックする位相同期装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase synchronization device that performs phase locking at high speed when the phase of an input horizontal synchronization signal of a television signal as an input signal changes by one line or several lines.
従来の位相同期装置を第１図に示す。A conventional phase synchronization device is shown in FIG.
図において、１は入力水平同期信号の入力端子、２は位
相比較器、３はＬＰＦ、４は電圧制御発振器、５は１／
Ｎの分周器、６は入力信号に同期した信号の出力端子で
ある。このような構成において、入力端子１の入力水５
平同期信号ｆｒｅｆと１／Ｎの分周器５の出力信号ｆ
ｏ／Ｎとを位相比較器２で比較し、両方の信号の位相差
により、その位相差に比例したパルス幅を持つパルスを
発生し、そのパルスはＬＰＦ３で積分され直流となる。In the figure, 1 is the input terminal of the input horizontal synchronization signal, 2 is the phase comparator, 3 is the LPF, 4 is the voltage controlled oscillator, and 5 is the 1/1
N frequency divider 6 is an output terminal for a signal synchronized with the input signal. In such a configuration, the input water 5 of the input terminal 1
Flat synchronization signal fref and output signal f of frequency divider 5 of 1/N
o/N is compared by a phase comparator 2, and based on the phase difference between both signals, a pulse having a pulse width proportional to the phase difference is generated, and the pulse is integrated by an LPF 3 and becomes a direct current.
この直流電圧により電圧制御０ 御発振器４が周波数ｆ
。で発振し、分周器５で１／Ｎ分周したのち位相比較器
２で比較する。そして位相差が００になると上記のルー
プは安定状態となり、入力端子１の入力水平同期信号ｆ
ｒｅｆと出力端子６の出力信号ｆ。／Ｎの信号がｆｒｅ
ｆ１５＝ｆ０／Ｎとなり位相ロックする。しかしながら
、このような位相同期装置では位相比較器２の出力をＬ
ＰＦ３で積分しているので、入力水平同期信号の位相が
その位相同期範囲を越えて急激に変化した場合には急速
に追随できず、Ｊ その変化の影響が遅くまで残り、例
えばノイズの多いＶＴＲのように疑似同期が発生して水
平周波数が急激に変化する信号を扱う方式には不適当で
あつた。本発明はこのような従来の問題点を除去したも
２５ので、テレビジョン信号の入力水平同期信号が１ラ
イン又は数ラインの間、位相同期範囲（以下単に範囲と
いう）を越えて、その後越える以前の位相に戻るか、又
は範囲内に位相が戻つた場合、その越えたことを検出回
路で検出し、その信号で位３０相同期回路の位相同期範
囲内に設定された固定電圧に切り換え、その電圧に対応
した発振周波数を範囲を越えている間一定とし、入力水
平同期信号の周波数が周波数変動幅を定めた範囲内に入
ると同期に、入力水平同期信号の周波数に追随するよ３
５うにしたものである。This DC voltage controls the voltage 0 and the control oscillator 4 has a frequency f
. The frequency is divided by 1/N by the frequency divider 5, and then compared by the phase comparator 2. When the phase difference becomes 00, the above loop becomes stable, and the input horizontal synchronization signal f of input terminal 1
ref and the output signal f of the output terminal 6. /N signal is fre
f15=f0/N, and the phase is locked. However, in such a phase synchronization device, the output of the phase comparator 2 is
Since integration is performed by PF3, if the phase of the input horizontal synchronization signal suddenly changes beyond its phase synchronization range, it cannot be followed rapidly, and the effect of the change remains until late, for example, when using a noisy VTR. This method was unsuitable for handling signals such as those in which pseudo synchronization occurs and the horizontal frequency changes rapidly. The present invention eliminates such conventional problems25, so that the input horizontal synchronization signal of the television signal exceeds the phase synchronization range (hereinafter simply referred to as range) for one line or several lines, and then before exceeding it. When the phase returns to or within the range, the detection circuit detects that the phase has been exceeded, and uses that signal to switch to a fixed voltage set within the phase locking range of the phase 30 phase locking circuit. The oscillation frequency corresponding to the voltage is kept constant while it exceeds the range, and when the frequency of the input horizontal synchronizing signal falls within the range where the frequency fluctuation range is determined, it synchronously follows the frequency of the input horizontal synchronizing signal.
5 sea urchin.
以下本発明の一実施例を図面により詳細に説明する。第
２図は本発明の一実施例を示すブ頭ノク図で２１は入力
水平同期信号（Ｆｒｅｆ）の入力端子、２２は位相比較
器、２３は増幅器、２４は電圧制御発振器（ＶＣＯ）、
２５は１／Ｎの分周器、２６は入力水平同期信号が位相
同期範囲を越えたことを検出する検出器、２７は入力信
号に同期した信号の出力端子で、これらで位相同期回路
を構成している。An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention, where 21 is an input terminal for an input horizontal synchronizing signal (Fref), 22 is a phase comparator, 23 is an amplifier, 24 is a voltage controlled oscillator (VCO),
25 is a 1/N frequency divider, 26 is a detector that detects that the input horizontal synchronization signal exceeds the phase synchronization range, and 27 is an output terminal for a signal synchronized with the input signal, and these constitute a phase synchronization circuit. are doing.
なお、第３図は位相比較器２２の詳細図で、３１はラン
プ波形成形回路、３２は第１のスイツチ回路、３３は第
２のスイツチ回路、Ｃ１はコンデンサ、Ｅ１は電池であ
る。また、第４図は本発明装置のタイムチヤートを示し
、ａは検出信号、ｂは入力水平同期信号（Ｆ，ｅｆ）、
ｃは比較器入力電肝、ｄは位相比較器２２の入力信号（
ＦｄｅＯ）を示す。次に、本発明に係る動作を第２図、
第３図及び第４図により説明する。FIG. 3 is a detailed diagram of the phase comparator 22, in which 31 is a ramp waveform shaping circuit, 32 is a first switch circuit, 33 is a second switch circuit, C1 is a capacitor, and E1 is a battery. FIG. 4 shows a time chart of the device of the present invention, where a is a detection signal, b is an input horizontal synchronizing signal (F, ef),
c is the comparator input voltage, d is the input signal of the phase comparator 22 (
FdeO). Next, the operation according to the present invention is shown in FIG.
This will be explained with reference to FIGS. 3 and 4.
入力端子２１の人力水平同期信号Ｆｒｅｆと１／Ｎ分周
器２５の出力信号（ＦＯ／Ｎ−ＦｄｅＯ）を位相比較器
２２で比較している。A phase comparator 22 compares the human-powered horizontal synchronizing signal Fref at the input terminal 21 and the output signal (FO/N-FdeO) of the 1/N frequency divider 25.
位相比較入力電圧は第４図ｃに示すような電圧波形であ
り、入力水平同期信号Ｆｒｅｆの周波数変動に対して出
力信号Ｆ。／Ｎが一定の周波数変動幅で追随するように
比較器電圧波形をｍからｎの範囲に限定し、位相同期範
囲を定めている。また電圧制御発振器２４では第４図Ｃ
Ｏ）Ｙに示すような位相比較出力電圧により上記の位相
同期範囲内の電圧に対する周波数Ｆ。を発振する。また
、１／Ｎ分周器２５では発振周波数Ｆ。を１／Ｎに分周
し、出力端子２７に出力信号Ｆ。／Ｎを送出し、もう一
方は位相比較器２２の入力信号ＦｄｅＯとなる。今、第
４図におけるＡ−Ｂ間のように数ラインの間、第４図ｂ
の入力水平同期信号Ｆｒｅｆが位相同期範囲を越えた場
合、位相比較器２２内の各スイツチ（第３図参照）の動
作を次に述べる。The phase comparison input voltage has a voltage waveform as shown in FIG. The comparator voltage waveform is limited to the range from m to n so that /N follows within a constant frequency fluctuation range, and the phase synchronization range is determined. In addition, in the voltage controlled oscillator 24, as shown in FIG.
O) Frequency F for voltages within the above phase locking range with the phase comparison output voltage as shown in Y. oscillates. Further, the 1/N frequency divider 25 has an oscillation frequency F. is divided into 1/N, and an output signal F is output to the output terminal 27. /N, and the other becomes the input signal FdeO of the phase comparator 22. Now, between several lines such as between A and B in Figure 4,
The operation of each switch (see FIG. 3) in the phase comparator 22 when the input horizontal synchronization signal Fref exceeds the phase synchronization range will be described below.
先ず、入力水平同期信号Ｆｒｅｆが来ると、第１のスイ
ツチ回路３２が閉じて、ある電圧がコンデンサＣ１に充
電される。然し、入力水平同期信号Ｆｒｅｆが位相同期
範囲を越えた場合（第４図におけるＡ−Ｂ間）はコンデ
ンサＣ１の充電電圧が第４図ＣＯＲ−Ｓの電圧となり、
検出器２６が動作する。この検出器２６の動作により検
出信号が出力され、その信号によつて第２のスイツチ回
路３３が動作して（第２のスイツチ回路３３が動作する
ときは第１のスイツチ回路３２は必ず開となる）、Ｅ１
の電圧がコンデンサＣ，に充電され、第４図ＣＯＹのよ
うに変化する。なお電圧Ｅ１は水平同期信号の基準周波
数になる電圧にセツトされている。このように入力水平
同期信号が位相同期範囲を１ライン又は数ライン越えた
場合は上記の動作を繰り返し、周波数変動が変動幅内に
入ると同時に、その周波数に追随する。First, when the input horizontal synchronization signal Fref arrives, the first switch circuit 32 is closed and a certain voltage is charged to the capacitor C1. However, when the input horizontal synchronization signal Fref exceeds the phase synchronization range (between A and B in Figure 4), the charging voltage of capacitor C1 becomes the voltage of COR-S in Figure 4,
Detector 26 is activated. A detection signal is output by the operation of this detector 26, and the second switch circuit 33 is operated by that signal (when the second switch circuit 33 operates, the first switch circuit 32 is always open). ), E1
The voltage is charged to the capacitor C, and changes as shown in FIG. 4 COY. Note that the voltage E1 is set to a voltage that corresponds to the reference frequency of the horizontal synchronizing signal. In this way, when the input horizontal synchronization signal exceeds the phase synchronization range by one line or several lines, the above operation is repeated, and as soon as the frequency fluctuation falls within the fluctuation range, the frequency is followed.
以上説明したように、本発明によれば位相同期範囲内で
は入力水平同期信号の周波数変動に対して追随し、入力
水平同期信号が位相同期範囲を越えた場合は、その越え
たことを検出器で検出し、その検出信号により第２のス
イツチ回路を動作してコンデンサをＥ１の電圧に充電し
ている。As explained above, according to the present invention, within the phase synchronization range, the frequency fluctuation of the input horizontal synchronization signal is followed, and when the input horizontal synchronization signal exceeds the phase synchronization range, the detector detects that the input horizontal synchronization signal exceeds the phase synchronization range. The detection signal operates the second switch circuit to charge the capacitor to the voltage E1.
そして周波数変動が範囲内に入るまで上記動作を続け、
範囲内に入ると同時に、その周波数に追随するよう動作
をする。従つて、位相同期範囲を１ライン又は数ライン
越えても、この間はＥ１電圧の周波数で動作し、範囲内
にその周波数が入ると同時に位相ロツクが行われるので
ランダムノイズ、ドロツプアウトノイズに対しては非常
に効果がある。特に上記ノイズの多い簡易ＶＴＲ等にも
利用して効果がある。Then, continue the above operation until the frequency fluctuation falls within the range,
As soon as it comes within range, it will begin to follow that frequency. Therefore, even if the phase locking range is exceeded by one or several lines, the device will operate at the E1 voltage frequency during this time, and phase locking will be performed as soon as the frequency falls within the range, so random noise and dropout noise will not occur. It is very effective against. It is particularly effective to use the above-mentioned simple VTR with a lot of noise.
第１図は従来の位相同期装置を示すプロツク図、第２図
は本発明位相同期装置の一実施例を示すプロツク図、第
３図は位相比較器の詳細図、第４図は本発明位相同期装
置のタイムチヤートを示す図である。
２１・・・・・・入力端子、２２・・・・・・位相比較
器、２３・・・・・・増幅器、２４・・・・・・電圧制
御発振器、２５・・・・・・１／Ｎ分周器、２６・・・
・・・検出器、３１・・・・・・ランプ波形成形回路、
３２・・・・・・第１のスイツチ回路、３３・・・・・
・第２のスイツチ回路。FIG. 1 is a block diagram showing a conventional phase synchronization device, FIG. 2 is a block diagram showing an embodiment of the phase synchronization device of the present invention, FIG. 3 is a detailed diagram of a phase comparator, and FIG. 4 is a block diagram of a phase synchronization device of the present invention. It is a figure which shows the time chart of a synchronization device. 21...Input terminal, 22...Phase comparator, 23...Amplifier, 24...Voltage controlled oscillator, 25...1/ N frequency divider, 26...
...Detector, 31...Ramp waveform shaping circuit,
32...First switch circuit, 33...
-Second switch circuit.
Claims (1)
路で、入力水平同期信号の周波数変動の一定幅に追随す
るよう位相同期範囲を定めた回路において、その範囲を
越えたことを検出する検出回路を設け、その範囲を１ラ
イン又は数ライン越えた場合、位相同期回路の発振周波
数を位相同期範囲内の一定周波数に発振するよう設定し
た固定電圧を設け、検出回路からの検出信号によりその
固定電圧に切り換え位相同期回路の発振周波数を、位相
同期範囲を越えている間一定とし、入力水平同期信号の
周波数が周波数変動幅を定めた範囲内に入ると同時に、
入力水平同期信号の周波数に追随するようにしたことを
特徴とする位相同期装置。1. A circuit that performs phase synchronization with the horizontal synchronization signal of a television signal, which has a phase synchronization range determined to follow a certain width of frequency fluctuation of the input horizontal synchronization signal, and a detection circuit that detects when the range is exceeded. A fixed voltage is set to oscillate the oscillation frequency of the phase-locked circuit to a constant frequency within the phase-locked range when the range is exceeded by one line or several lines, and the detection signal from the detection circuit is used to adjust the fixed voltage to the fixed voltage. The oscillation frequency of the switching phase synchronization circuit is kept constant while exceeding the phase synchronization range, and as soon as the frequency of the input horizontal synchronization signal enters the range in which the frequency fluctuation width is determined,
A phase synchronization device characterized in that it follows the frequency of an input horizontal synchronization signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4975079A JPS5915235B2 (en) | 1979-04-24 | 1979-04-24 | phase synchronizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4975079A JPS5915235B2 (en) | 1979-04-24 | 1979-04-24 | phase synchronizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55141869A JPS55141869A (en) | 1980-11-06 |
| JPS5915235B2 true JPS5915235B2 (en) | 1984-04-07 |
Family
ID=12839849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4975079A Expired JPS5915235B2 (en) | 1979-04-24 | 1979-04-24 | phase synchronizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5915235B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5966269A (en) * | 1982-10-07 | 1984-04-14 | Oki Electric Ind Co Ltd | Frequency stabilizing system |
| JPS61113482U (en) * | 1984-12-26 | 1986-07-17 | ||
| JPS6218873A (en) * | 1985-07-17 | 1987-01-27 | Victor Co Of Japan Ltd | Oscillation frequency control voltage generating circuit of horizontal deflecting and oscillating circuit |
-
1979
- 1979-04-24 JP JP4975079A patent/JPS5915235B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55141869A (en) | 1980-11-06 |
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