JPS60182820A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To improve the response while eliminating a steady-state phase error by detecting an error between an input frequency and a reference frequency in a PLL circuit to add a correction voltage to a filter output of a PLL loop. CONSTITUTION:A frequency comparator 6 obtaining an error between the reference frequency of a crystal oscillator 7 and the input frequency is provided to the PLL circuit where a feedback loop is made up of a phase comparator 1, a filter 2, a voltage controlled oscillator 3 and a frequency divider 4 and which is oscillated in synchronization with the change in the input frequency, and the error is fed to a control voltage of a voltage controlled oscillator VCO3 as a feedforward signal. Thus, the steady-state phase error is eliminated and it is possible to improve the response against input frequency fluctuation.

Description

Detailed Description of the Invention [8] Technical Field of the Invention The present invention is used in a demodulator that demodulates digital signals written on the disk surface of a magnetic disk or optical disk device, and is used to demodulate a demodulated signal generated by rotational fluctuations of the disk. This invention relates to a phase-locked loop circuit that compensates for frequency changes.

(b) Prior Art and Problems Magnetic disks and optical disk devices read digital signals of a constant frequency that have been written in advance into a gap provided in the front of the data area on the disk surface. The information written in the data area is read using the signal as a synchronization signal. When reading this information, even if the frequency of the signal written on the disk surface changes due to rotational fluctuations of the disk drive motor, a demodulation oscillator (phase-locked loop circuit) synchronized with this is used to compensate for the rotational fluctuation. and
Conventionally, a phase-locked loop circuit as shown in the block diagram of FIG. 1 has been used.

FIG. 1 shows a block diagram of an example of such a phase-locked loop circuit, which includes a phase comparator 1, a filter 2, a voltage controlled oscillator (hereinafter referred to as Vco) 3, and a frequency divider 4.
constitutes a feedback loop. In this operation, a digital signal A previously written in the gear section of the disk is read out and input to the input terminal a of the phase comparator 1.

At the other input terminal of the phase comparator 1, the output digital signal B of the VCO 3 is divided by a frequency divider 4, and the digital signal A is
A digital signal C having the same frequency is input. The phase comparator 1 compares the phases of the input digital signals A and C, detects a phase difference, and outputs the phase error signal to the filter 2. Filter 2 converts the input phase error signal into a corresponding voltage value. In other words, for example, when the phase error is 0, it becomes Ov・, and when the phase of digital signal A is ahead with respect to digital signal C, it becomes a positive potential.
On the other hand, if there is a delay, a negative potential is output, and a voltage value proportional to the phase lead/delay amount is output.

This phase difference voltage is input to VCO3. The VCO 3 operates to match the frequency of the input digital signal A (hereinafter referred to as input frequency) fa by the input phase difference voltage, and this output digital signal E is input to the frequency divider 4.
The frequency is divided by the frequency divider 4 and inputted to the input terminal of the phase comparator 1. The above-described operation is performed in response to the input signal A by a phase-locked loop circuit connected in a loop.

This phase-locked loop circuit has an input frequency fa of V
When the center frequency of CO3 deviates from the center frequency, the VCO3 operates to match the input frequency fa, so the phase comparator I
always has a phase error. On the other hand, in the conventional example, as shown in FIG. 1, an integrating circuit 5 that integrates the phase error is attached between the output terminal of the phase comparator 1 and the filter 2, and a circuit that integrates the phase error 2 feedback signal is added to the output of filter 2 to resolve the steady phase error. However, when a fixed length recording method is used in a recording device such as a magnetic disk or an optical disk device, the phase-locked loop circuit must respond at high speed to the next data area signal. However, the above-mentioned phase-locked loop circuit has the disadvantage that it takes a long time to respond to such a request, making it unsuitable.

(0) Object of the Invention An object of the present invention is to provide a phase-locked loop circuit that eliminates steady phase errors and has good responsiveness to discontinuous signal input.

((11) Configuration of the Invention According to the present invention, a feedback loop is configured by a phase comparator, a filter, a voltage controlled oscillator, and a frequency divider, and the feedback loop is synchronized with changes in the input frequency to the phase comparator. In the oscillating phase-locked loop circuit, a frequency comparator is added between the signal input terminal of the phase comparator and the signal output terminal of the filter, and the frequency comparator is configured to differentiate between the input frequency and the reference frequency of the reference signal generator. This is achieved by a phase-locked loop circuit characterized in that it detects an error between the two and generates a correction voltage for correcting the error frequency, and adds it to the phase error output voltage of the filter.

(81st Embodiment of the Invention Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a phase-locked loop circuit according to one such embodiment. The difference from the conventional phase-locked loop circuit shown in FIG. 1 is that a frequency comparator 6 is newly provided to calculate the error between the reference frequency and the input frequency fa. That is, it is not a phase synchronized circuit with only feedback, but an error between the reference frequency and the input frequency fa is added to the control voltage of the VCO 3 as a feedforward signal.

Fig. 3 is a block diagram showing an example configuration of a frequency comparator, Fig. 4 is a block diagram of a timing generation circuit used in the frequency comparator, and Fig. 5 shows waveforms of input and output signals of the timing generation circuit. 6 shows a characteristic diagram showing the relationship between the control voltage of the VCO and the oscillation frequency, and FIG. 7 shows a characteristic diagram of the frequency comparator.

The frequency comparator 6 of this embodiment uses a digital signal to determine the period in order to eliminate errors in the input frequency with respect to the reference frequency. That is, the reference signal generator 7 made of a crystal oscillator operates at the frequency of the input digital signal A, that is, the input frequency fa.
The frequency (reference frequency) N times that of the reference signal F (Fig. 5 F
reference). This reference signal F is supplied to the counter 9,
10 is input. The counters 9 and 10 are supplied with a clear pulse H outputted from the timing generation circuit 8 (see H in FIG. 5).
As a result, the count number up to now is cleared and the newly input reference signal F is counted during the cycle time of the input frequency fa. The timing generation circuit 8 is composed of a combination of four flip-flop circuits 81 to 84 and an inverter 85 as shown in FIG. This count output is input to the launch circuit 11.12. Launch circuit 11.1
2 temporarily stores the count output, and a timing generation circuit 8
The stored contents, that is, the count output, are controlled by the clock signal G (see FIG. 5 G) output from the ROM 13.
Output to. The ROM 13 has a conversion table in which an error signal corresponding to the error amount between the reference signal amount counted during the cycle time of the reference frequency and the reference signal amount counted during the cycle time of the input frequency is written in advance. An error signal corresponding to the input count output is output based on the conversion table. The output error signal is digital
input to the analog converter (D/A converter) 14,
It is generated as a voltage with the relationship shown in the figure. This generated voltage is O volts when the input frequency matches the reference frequency, and the control voltage (Ec) vs. oscillation frequency (f) characteristics of VCO3 shown in Figure 6 for the input frequency below the reference frequency. This is a positive or negative voltage that matches the oscillation frequency of the VCO with the reference frequency. However, if the input frequency changes significantly, the control voltage ([!c) is regulated at minimum and maximum values as shown in FIG. 7 so that the control voltage does not deviate from the target allowable frequency. Therefore, data bits from which a voltage having the characteristics as shown in FIG. 7 can be obtained are inputted to the ROM 13 through the D/A converter 14.

As mentioned above, by adding the frequency comparator 6 and applying its output, that is, the output control voltage Ec of the D/A converter 14, to the VCO as a feedforward signal,
The stationary phase error can be completely eliminated and the VCO
3 outputs an oscillation frequency that is responsive to large frequency fluctuations.

Although the third embodiment is configured to process an 8-bit digital signal, the number of counters and latch circuits can be changed depending on the number of bits of the digital signal.

(f) Effects of the Invention As is clear from the above description, according to the present invention, it is possible to obtain a phase-locked loop circuit that eliminates steady-state phase errors and has good responsiveness to input frequency fluctuations.

[Brief explanation of the drawing]

Figure 1 shows the conventional phase-locked loop circuit.
2 is a block diagram showing an example configuration of an embodiment of a phase-locked loop circuit according to the present invention, FIG. 3 is a block diagram showing an example of a frequency comparison circuit in this embodiment, and FIG. 4 is a block diagram showing an example of a frequency comparison circuit according to the present invention. 5 is a block diagram of a timing generation circuit used in the timing generation circuit. FIG. 5 is a diagram showing the waveforms of the input and output signals of the timing generation circuit, FIG. Figure 7 shows a characteristic diagram of the frequency comparator. In the figure, 1 is a phase comparator, 2 is a filter, 3 is a voltage controlled oscillator (VCO), 4 is a frequency divider, 5 is an integration circuit,
6 is a frequency comparator, 7 is a crystal oscillator, 8 is a timing pulse generation circuit, 9. IO is a counter, 11 and 12 are latches, 13 is a ROM, 14 is a digital/analog converter, 81 to 84 are flip-flop circuits, and 85 is an inverter.

Claims (1)

[Claims] In a phase-locked loop circuit that configures a feedback loop with a phase comparator, a filter, a voltage-controlled oscillator, and a frequency divider, and oscillates in synchronization with changes in the input frequency to the phase comparator, the signal input terminal of the phase comparator A frequency comparator is added between the input frequency and the signal output terminal of the filter, and the frequency comparator detects an error between the input frequency and the reference frequency of the reference signal generator and generates a correction voltage for correcting the error frequency. A phase locked loop circuit characterized in that the phase error is generated and added to the phase error output voltage of the filter.