JPS6249663B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demodulation circuit for stored data in a magnetic storage device such as a magnetic disk device, magnetic drum device, or magnetic tape device.

Conventional demodulation circuits for input signals in which data pulses and clock pulses are generated alternately at a fixed period use monostable circuits or VFOs.
PLL using (Variable Frequency Oscilator)
(Phase Locked Loop) circuits are known. However, all of these circuits perform analog control and are less stable than digital circuits. In addition, data demodulation circuits using monostable circuits cannot cope with fluctuations in the moving speed of the magnetic storage medium and peak shifts, so it is necessary to increase the number of monostable circuits or use logic circuits to compensate.On the other hand, in PLL, phase detection circuit, low pass filter and
It requires a complicated analog circuit such as a VCO (Voltage Control Oscillator), and it also has drawbacks such as a long time from when an input signal is applied until synchronization is completed, that is, a long pull-in time.

The present invention eliminates the above-mentioned drawbacks, and the above-mentioned PLL
The purpose of this invention is to improve the reliability of magnetic storage devices by configuring data demodulation circuits using logic circuits as much as possible while incorporating the advantages of this method, by digitalizing and simplifying the circuits.

For this reason, the present invention digitally detects the phase difference between an ideal input signal and an actual input signal using a counter that repeats counting operations at the cycle of an ideal input signal with no fluctuations.
Memory) or PLA (Program Logic Array)
By generating a correction value according to the phase difference and setting it in the counter, the cycle of the counting operation is changed, and the window width of the input signal is set to match the time of this cycle. The input signal is placed at the center of the window.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a demodulation circuit according to the present invention, and FIG. 2 is a time chart showing the operation of its main parts. In Fig. 1, the file data reproduction signal FD from the storage medium is transmitted to the differentiating circuit 1.
The differential signal a is supplied to one of the inputs of the data clock separation circuit 2 and the ROM 3.
The ROM 3 generates a correction value signal LD of various bit patterns on its output line in accordance with the multiple bit information applied to its input, and also generates a set signal on a line 5 to set this correction value signal LD in the counter 4. do. The counter 4 repeats the counting operation at the same period as the period T of the ideal input signal when there is no fluctuation. In response to an ideal input signal, the counter 4 ideally performs a counting operation with the time relationship shown in FIG. 2b. The contents of counter 4 are provided to ROM 3 and decoder 6. When the content of the counter 4 is 0, the decoder 6 sets the set signal c of the flip-flop 7.
is supplied, and when the counter 4 reaches n, a reset signal d is supplied. The set side output e of the flip-flop 7 is sent to the data clock separation circuit 2 as a window of file data FD.

The output signal a of the differentiating circuit 1 is the file data FD.
Between the clock signal P and the data signal D
including. However, at this stage it is not clear which is the clock and which is the data. When this differential signal a is obtained at an ideal interval T, the counter 4
The contents of the counter 4 are n/2, and the correction value signal LD for correcting the contents of the counter 4 is not sent from the ROM 3. When the interval of the differential signal a changes so as to be wider than T, the content of the counter 4 when the differential signal a is obtained is greater than n/2. Therefore, in this case, the differential signal a shifts to the right of the center of the window e. In order to bring such a differential signal a to the center of the window e, the reset of the flip-flop 7 can be delayed to widen the width of the window. For that, counter 4
It is necessary to slow down the time it takes for the counter 4 to count up to n, but this can be done by correcting the contents of the counter 4 to a value smaller than n/2.
Therefore, the content of the counter 4 when the actual differential signal is obtained and the differential signal a at an ideal interval that does not fluctuate.
If the correction value of the counter 4 is determined uniquely according to the difference between the content of the counter 4 and the content of the counter 4 when . It becomes wider or narrower as it approaches the center.
If the content of counter 4 is determined to be a certain number when an ideal differential signal is obtained, the content of counter 4 can be directly correlated with the above correction value, so that the content of counter 4 is smaller than n/2. If n ₁ is large, a correction value of (n-n ₁ ), for example, is sent from the ROM 3 and is set in the counter 4.
The counter 4 continues counting from this (n-n ₁ ), and when it counts up by n ₁ and reaches n, the flip-flop 7 is reset and the window e is divided. In this window e, counter 4 is (n
−n ₁ ), the window becomes wider than the ideal window by the time required to count up to n ₁ .

When the interval of the differential signal a changes to become narrower than T, the content of the counter 4 when this differential signal is obtained is smaller than n/2. Therefore, in this case, in order to bring the differential signal to the center of the window e, the content of the counter 4 must be corrected to a value greater than n/2 to narrow the width of the window e. If the content of the counter 4 when the differential signal a is obtained is _n2 , then the counter 4 has
A correction value (n-n ₂ ) is set from the ROM 3, and when the counter 4 increments to n, the flip-flop 7 is reset and the window e is divided.

As described above in detail based on the embodiments, according to the present invention, even if an input signal arrives at a period different from the period of the ideal input signal, the window is adjusted so that the input signal and the window have a predetermined phase relationship. The width is adjusted, and this adjustment is performed by a counter that repeats counting operation at the cycle of the ideal input signal and a ROM that generates a correction value based on the value of the counter when the actual input signal is obtained. This is done digitally depending on the phase difference between the input signal and the ideal input signal. These simplify the data demodulation circuit and improve reliability. Further, the phase of the actual input signal and its data window can be matched in a short time.

Note that the present invention is not limited to the above embodiments. For example, ROM3 is a PLA that sends out specific output information that is uniquely defined according to input information.
(Program Logic Array) can be used instead.
Furthermore, the count value of the counter 4 mentioned in the explanation of the embodiment can be set arbitrarily. 4 and the window was divided when counter 4 was n, but by changing the configuration of ROM 3, it is also possible to set the former to n and the latter to n/2, and furthermore You can also choose any value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a time chart used to explain FIG. 1. 1...Differential circuit, 3...ROM, 4...Counter, 6
…decoder.

Claims (1)

[Claims] 1. When a data pulse is inserted between clock pulses and there is no temporal variation, the time interval between adjacent clock pulses is T.
In a demodulation circuit that demodulates data from an input signal into which a data pulse is inserted, a correction value from a correction value generation means and a signal for setting this correction value as an initial value are input, and the time T is set as a standard value. a counter whose counting period is inputted with the input signal and the output signal of the counter, and with a count value of the counter when a clock pulse and a data pulse are inputted when there is no temporal variation in the input signal as a reference; A correction value corresponding to the difference between the current count value output from the counter and this reference count value is stored, and the count value of the counter and the reference count value differ when a clock pulse and a data pulse are input. and a correction value generating means that generates a signal for setting this correction value as an initial value of the counter; and a correction value generating means that inputs an output signal of the counter, and is reset when the count value reaches a predetermined value, and a predetermined value whose count has advanced beyond this. means for generating a window that is set when a value is reached, and the predetermined values are values for generating a window centered on each pulse of the clock pulse and the data pulse; 1. A demodulation circuit characterized in that the counting period of a counter changes, thereby changing the reset timing of a window, thereby generating a window centered on each pulse of a clock pulse and a data pulse.