JPS54151014A - Demodulating system - Google Patents

Demodulating system

Info

Publication number
JPS54151014A
JPS54151014A JP5885378A JP5885378A JPS54151014A JP S54151014 A JPS54151014 A JP S54151014A JP 5885378 A JP5885378 A JP 5885378A JP 5885378 A JP5885378 A JP 5885378A JP S54151014 A JPS54151014 A JP S54151014A
Authority
JP
Japan
Prior art keywords
signal
input signal
fluctuations
counter
rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5885378A
Other languages
Japanese (ja)
Other versions
JPS6249663B2 (en
Inventor
Masao Umemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP5885378A priority Critical patent/JPS54151014A/en
Publication of JPS54151014A publication Critical patent/JPS54151014A/en
Publication of JPS6249663B2 publication Critical patent/JPS6249663B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To synchronize the system to the fluctuations, etc. of the moving speed of memory media rapidly and accurately with a simple constitution by reading out the correction signal of a ROM according to reproduction signal and controlling a counter which counts the ideal input signal periods free from fluctuations.
CONSTITUTION: The reproduced file data from a recording medium wherein data pulses and clock pulses are produced alternately at a fixed period are applied via differentiation circuit 1 to ROM 3. This causes the correction signal for the ideal input signal period of the ROM 3 to be read out according to the reproduction input signal. This signal controls a counter 4 which counts the ideal input signal periods. Hence, when the set and reset of an FF 7 are controlled via decoder 6 by the count valve of the counter 4, the input signal is synchronously locked so as to position at the center of the window signal according to the fluctuations of the moving speed of the recording medium and the fluctuations of peak shift, by way of an AND gate 2 which is opened by the signal owing to the set signal of the FF 7.
COPYRIGHT: (C)1979,JPO&Japio
JP5885378A 1978-05-19 1978-05-19 Demodulating system Granted JPS54151014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5885378A JPS54151014A (en) 1978-05-19 1978-05-19 Demodulating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5885378A JPS54151014A (en) 1978-05-19 1978-05-19 Demodulating system

Publications (2)

Publication Number Publication Date
JPS54151014A true JPS54151014A (en) 1979-11-27
JPS6249663B2 JPS6249663B2 (en) 1987-10-20

Family

ID=13096234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5885378A Granted JPS54151014A (en) 1978-05-19 1978-05-19 Demodulating system

Country Status (1)

Country Link
JP (1) JPS54151014A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5794915A (en) * 1980-12-03 1982-06-12 Matsushita Electric Ind Co Ltd Demodulating circuit
JPS57103115A (en) * 1980-12-18 1982-06-26 Matsushita Electric Ind Co Ltd Control circuit of magnetic recorder and reproducer
JPS5897116A (en) * 1981-12-02 1983-06-09 スタンダ−ド・マイクロシステムズ・コ−ポレ−シヨン Improvement in floppy disc data separator
JPS58170225A (en) * 1982-03-31 1983-10-06 Fujitsu Ltd Self-clock device
JPS62137921A (en) * 1985-12-11 1987-06-20 Fujitsu Ltd Pll control system
JPH02501526A (en) * 1988-01-25 1990-05-24 ユニシス　コーボレーシヨン Data bit detector for fiber optic systems

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5430011A (en) * 1977-08-10 1979-03-06 Hitachi Ltd Phase synchronous oscillator of digital type

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5430011A (en) * 1977-08-10 1979-03-06 Hitachi Ltd Phase synchronous oscillator of digital type

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5794915A (en) * 1980-12-03 1982-06-12 Matsushita Electric Ind Co Ltd Demodulating circuit
JPS57103115A (en) * 1980-12-18 1982-06-26 Matsushita Electric Ind Co Ltd Control circuit of magnetic recorder and reproducer
JPS5897116A (en) * 1981-12-02 1983-06-09 スタンダ−ド・マイクロシステムズ・コ−ポレ−シヨン Improvement in floppy disc data separator
JPS58170225A (en) * 1982-03-31 1983-10-06 Fujitsu Ltd Self-clock device
JPS62137921A (en) * 1985-12-11 1987-06-20 Fujitsu Ltd Pll control system
JPH02501526A (en) * 1988-01-25 1990-05-24 ユニシス　コーボレーシヨン Data bit detector for fiber optic systems

Also Published As

Publication number Publication date
JPS6249663B2 (en) 1987-10-20

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