JPS5794915A - Demodulating circuit - Google Patents
Demodulating circuitInfo
- Publication number
- JPS5794915A JPS5794915A JP55171222A JP17122280A JPS5794915A JP S5794915 A JPS5794915 A JP S5794915A JP 55171222 A JP55171222 A JP 55171222A JP 17122280 A JP17122280 A JP 17122280A JP S5794915 A JPS5794915 A JP S5794915A
- Authority
- JP
- Japan
- Prior art keywords
- reproduced
- signal
- clock
- demodulation
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
Abstract
PURPOSE:To obtain a demodulated signal which has less errors in demodulation due to timing jitters by extracting a reproduced clock required for the demodulation by using a high-frequency clock whose frequency is set to a multiple of an original signal bit frequency and a reproduced MFM-modulated signal. CONSTITUTION:A reproduced MFM-modulated signal is inputted to an edge extracting circuit 20 to obtain a pulse, which rises and falls correspondingly, by a high-frequency clock having a period of one Nth (N>=1) of the bit period TO of an original signal. A counter circuit 23 obtains a reproduced clock which follows up the MFM modulated signal by the output of a preset-value generating circuit 24 passed through a counter circuit 21 for a ''101'' detection gate and a gate circuit 22. The output of a TO/2 delay counter 25 is inverted and inputted to a flip-flop 28 to obtain a demodulated signal by using the reproduced clock inputted to a clock terminal. Thus, the demodulation signal which has less errors in demodulation due to jitters is obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55171222A JPS5794915A (en) | 1980-12-03 | 1980-12-03 | Demodulating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55171222A JPS5794915A (en) | 1980-12-03 | 1980-12-03 | Demodulating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5794915A true JPS5794915A (en) | 1982-06-12 |
Family
ID=15919300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55171222A Pending JPS5794915A (en) | 1980-12-03 | 1980-12-03 | Demodulating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5794915A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61159841A (en) * | 1985-01-08 | 1986-07-19 | Sanyo Electric Co Ltd | Clock synchronizing system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5037414A (en) * | 1973-08-03 | 1975-04-08 | ||
JPS547246A (en) * | 1977-06-17 | 1979-01-19 | Honeywell Inf Systems | Digital information retrieving unit from large capacity memory |
JPS54151014A (en) * | 1978-05-19 | 1979-11-27 | Oki Electric Ind Co Ltd | Demodulating system |
-
1980
- 1980-12-03 JP JP55171222A patent/JPS5794915A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5037414A (en) * | 1973-08-03 | 1975-04-08 | ||
JPS547246A (en) * | 1977-06-17 | 1979-01-19 | Honeywell Inf Systems | Digital information retrieving unit from large capacity memory |
JPS54151014A (en) * | 1978-05-19 | 1979-11-27 | Oki Electric Ind Co Ltd | Demodulating system |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61159841A (en) * | 1985-01-08 | 1986-07-19 | Sanyo Electric Co Ltd | Clock synchronizing system |
JPH0344702B2 (en) * | 1985-01-08 | 1991-07-08 | Sanyo Electric Co |
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