JPS566568A - Sampling method for facsimile signal - Google Patents

Sampling method for facsimile signal

Info

Publication number
JPS566568A
JPS566568A JP8309079A JP8309079A JPS566568A JP S566568 A JPS566568 A JP S566568A JP 8309079 A JP8309079 A JP 8309079A JP 8309079 A JP8309079 A JP 8309079A JP S566568 A JPS566568 A JP S566568A
Authority
JP
Japan
Prior art keywords
circuit
signal
sampling
clock
varying point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8309079A
Other languages
Japanese (ja)
Inventor
Hideji Yanase
Koji Ueda
Mitsugi Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP8309079A priority Critical patent/JPS566568A/en
Publication of JPS566568A publication Critical patent/JPS566568A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40Picture signal circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Facsimile Scanning Arrangements (AREA)
  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To reproduce a good picture which is free from the jitter effect, by selecting the two sets of sampling clocks having the different phases and then setting the varying point of the picture signal at the center of the sampling timing. CONSTITUTION:The picture signal extracted out of demodulator circuit 10 receives the shaping into the binary coded signal through waveform shaping circuit 11 to be then sent to sampling clock comparator circuit 2. Circuit 2 supplies the oscillation signal of oscillator circuit 13 to clock signal generating part 21 to produce pulse- type two sampling clocks S1 and S2 having the 180 deg.-phase difference plus sample signals J and K each. These clocks and signals are applied to AND circuits 21 and 22 along with picture signal varying point detecting output signal d of varying point detecting part 24. Then picture signal d near the varying point is sampled, and detection signals L1 and L2 are sent to clock selection circuit 4 through circuits 21 and 22. Here selected clock S1 or S2 plus signal d are applied to sampling circuit 14. As signal d is positioned at the area near the middle of S1 and S2, no effect of jitter is given at all by the selection of S1 or S2. This output is then applied to recording circuit 16 via interface circuit 15.
JP8309079A 1979-06-28 1979-06-28 Sampling method for facsimile signal Pending JPS566568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8309079A JPS566568A (en) 1979-06-28 1979-06-28 Sampling method for facsimile signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8309079A JPS566568A (en) 1979-06-28 1979-06-28 Sampling method for facsimile signal

Publications (1)

Publication Number Publication Date
JPS566568A true JPS566568A (en) 1981-01-23

Family

ID=13792474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8309079A Pending JPS566568A (en) 1979-06-28 1979-06-28 Sampling method for facsimile signal

Country Status (1)

Country Link
JP (1) JPS566568A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5813500A (en) * 1981-07-17 1983-01-25 Komatsu Ltd Controller for press
US4667246A (en) * 1984-04-25 1987-05-19 Canon Kabushiki Kaisha Image processing system
JPH01251106A (en) * 1988-03-31 1989-10-06 Samutaku Kk Start timing controller
US5014137A (en) * 1984-12-25 1991-05-07 Ricoh Company, Ltd. Method of generating an image scanning clock signal for an optical scanning device by selecting one of a plurality of out-of-phase clock signals

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5813500A (en) * 1981-07-17 1983-01-25 Komatsu Ltd Controller for press
JPH0353080B2 (en) * 1981-07-17 1991-08-13 Komatsu Mfg Co Ltd
US4667246A (en) * 1984-04-25 1987-05-19 Canon Kabushiki Kaisha Image processing system
US5014137A (en) * 1984-12-25 1991-05-07 Ricoh Company, Ltd. Method of generating an image scanning clock signal for an optical scanning device by selecting one of a plurality of out-of-phase clock signals
JPH01251106A (en) * 1988-03-31 1989-10-06 Samutaku Kk Start timing controller

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