JPS566569A - Sampling method for facsimile signal - Google Patents

Sampling method for facsimile signal

Info

Publication number
JPS566569A
JPS566569A JP8309179A JP8309179A JPS566569A JP S566569 A JPS566569 A JP S566569A JP 8309179 A JP8309179 A JP 8309179A JP 8309179 A JP8309179 A JP 8309179A JP S566569 A JPS566569 A JP S566569A
Authority
JP
Japan
Prior art keywords
circuit
clock
sampling
signal
clocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8309179A
Other languages
Japanese (ja)
Inventor
Hideji Yanase
Koji Ueda
Mitsugi Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP8309179A priority Critical patent/JPS566569A/en
Publication of JPS566569A publication Critical patent/JPS566569A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40Picture signal circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimile Scanning Arrangements (AREA)
  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To reproduce a good picture which is free from the jitter effect, by selecting the two sets of auxiliary sampling clocks of different phases and then setting the varying point of the picture signal at the center of the sampling timing. CONSTITUTION:The picture signal sent from demodulator circuit 10 receives the binary coding through waveform shaping circuit 11 to be sent to sampling clock comparator circuit 2. Circuit 2 produces auxiliary sampling clocks S1 and S2 of different phases by 180 deg. via oscillator circuit 13 and the clock signal generating part and then sampling signals J and K from clocks S1 and S2 each. These clocks and signals are then supplied to AND circuits 22 and 23 along with the signal sent from varying point detecting part 24. Then picture signal d near the varying point is sampled, and detection signals L1 and L2 corresponding to signal d are sent to clock selection circuit 4. Here clock S is selected to set the varying point of the picture signal at the center to be applied to sampling circuit 31 along with signal d. The clock is then sampled at circuit 31 and by main sample clock Sr to be supplied to recording device 16 through interface circuit 15.
JP8309179A 1979-06-28 1979-06-28 Sampling method for facsimile signal Pending JPS566569A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8309179A JPS566569A (en) 1979-06-28 1979-06-28 Sampling method for facsimile signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8309179A JPS566569A (en) 1979-06-28 1979-06-28 Sampling method for facsimile signal

Publications (1)

Publication Number Publication Date
JPS566569A true JPS566569A (en) 1981-01-23

Family

ID=13792502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8309179A Pending JPS566569A (en) 1979-06-28 1979-06-28 Sampling method for facsimile signal

Country Status (1)

Country Link
JP (1) JPS566569A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943857A (en) * 1987-04-24 1990-07-24 Hitachi, Ltd. Synchronizing circuit for an external signal and an internal sampling clock signal
US5014137A (en) * 1984-12-25 1991-05-07 Ricoh Company, Ltd. Method of generating an image scanning clock signal for an optical scanning device by selecting one of a plurality of out-of-phase clock signals

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5014137A (en) * 1984-12-25 1991-05-07 Ricoh Company, Ltd. Method of generating an image scanning clock signal for an optical scanning device by selecting one of a plurality of out-of-phase clock signals
US4943857A (en) * 1987-04-24 1990-07-24 Hitachi, Ltd. Synchronizing circuit for an external signal and an internal sampling clock signal

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