JPH0344702B2 - - Google Patents

Description

[Detailed description of the invention]

B) Industrial Application Field The present invention relates to a synchronization method for a receiver used in digital data transmission. B) Conventional technology Conventionally, when synchronizing the digital signal sent from the transmitter and the clock signal of the receiver, the direction and magnitude of the phase shift between the two signals has been studied, for example, as disclosed in Japanese Patent Application Laid-open No. 58-223944. There are two methods: a method that detects the phase shift and applies an appropriate correction, and a method that detects only the direction of the phase shift and applies a fixed amount of correction in an appropriate direction. C) Problems to be Solved by the Invention Incidentally, in such a synchronization system for digital data transmission, for example, a signal having a code rule such as a biphase code is used to monitor level change points that occur periodically according to the code rule. , the phase shift between the signal sent from the transmitting side and the clock signal was detected. Therefore, if there is noise on the transmission signal from the transmitting side, there is a risk that this peripheral surface may be mistakenly detected as a level change point that occurs periodically due to the code rule, and incorrect correction may be made, disturbing the synchronization state. It was hot. D) Means for solving the problem The present invention detects "H" and "L" levels at multiple detection points of the signal sent from the transmitting side, and outputs a large number of these levels. A majority logic circuit, a clock generation circuit that generates a clock signal, and a phase comparison circuit that detects the direction of phase shift between the clock signal from the clock generation circuit and the output from the majority logic circuit are provided. E) Effect: The phase comparator circuit detects the direction of phase shift between the output from the majority logic circuit and the clock signal from the clock generation circuit, and changes the generation state of the clock signal in the clock generation circuit. Therefore, even if the transmission signal contains noise, the phase shift with the clock signal can be detected accurately, and reliable synchronization can be achieved. f) Embodiment FIG. 1 is a block circuit diagram of a receiver used in the clock synchronization system of the present invention, in which numeral 1 indicates a 3-bit shift register that receives a transmission signal from the transmitting side, and a basic clock from an oscillator 2. The "H" and "L" levels of the transmission signal are sequentially read and shifted. 3 is a majority logic circuit which receives signals from each bit of the shift register 1 and outputs the higher level of "H" or "L". Reference numeral 4 denotes a variable frequency divider circuit that divides the basic clock from the oscillator 2. For example, the length of one bit of the biphasic code sent from the transmitting side is approximately adjusted to the length of 32 of the basic clocks. , the upper and lower frequency division states can be switched to, for example, 31 frequency division and 33 frequency division.
5 is a decoder that decodes the output of this frequency divider 4, and the output value of the variable frequency divider 4 is 8, 16, 24.
Signals φa, φb, and φc are output corresponding to the respective signals.
Reference numerals 6 and 7 indicate first and second flip-flop circuits whose data input terminals D receive the outputs of the majority logic circuit 3, and the timing terminals T of these first and second flip-flop circuits 6 and 7 are connected to the decoders described above, respectively. Signals φa and φb from 5 are input. 8 is the Q of the first and second flip-flop circuits 6 and 7.
This shows a gate that takes the exclusive OR of outputs, and its output is sent to the variable frequency divider circuit 4, which switches the frequency division output. That is, here, the first and second flip-flop circuits 6 and 7 and the gate 8 constitute a phase comparison circuit. In such a clock synchronization system, as described above, a biphase code with a length of about 32 clock pulses from the oscillator 2, for example, as shown in FIG. 2, is sent as a transmission signal from the transmitting side. This biphasic code is sequentially read into the 3-bit shift register 1 by the basic clock from the oscillator 2, and the majority logic circuit 3 checks the contents of each bit of the shift register 1 to determine which is more "H" or "L". The higher level signal is output. This eliminates noise in the transmission signal, specifically, noise up to one clock length of the basic clock of the oscillator 2. The output of the majority logic circuit 3 is transmitted to the first and second flip-flop circuits 6,
7 data input terminals D, these are the first,
The second flip-flop circuits 6 and 7 output the signals input to the data input terminal D from the output terminal Q at the timing of the timing signals ta and tb which are decoded by the decoder 5 from the outputs 8 and 16 of the variable frequency divider 4, respectively. . Upon receiving the outputs of these first and second flip-flop circuits 6 and 7, the gate circuit 8 adopts the exclusive logic and uses the output to output the variable frequency divider circuit 4.
Switches whether the divided output is divided by 31 or 33. That is, here, when the output of the gate 8 is "H", the bit end of the transmission data sent from the transmitting side is between the timings of Ta and Tb, so the signal tb from the variable frequency divider 4 is
The variable frequency divider circuit 4 divides the frequency by 31, thereby shortening the frequency division period. On the other hand, when the output of the gate 8 is "L", the bit end of the transmission signal sent from the transmission side is not between the timings of Ta and Tb, and the signal from the variable frequency divider 4 is Assuming that tb is advanced, the variable frequency divider 4 begins to divide the frequency by 33 and lengthens the frequency division period. In this type of clock synchronization method, the direction of the phase shift between the noise-removed transmission signal and the clock signal is detected and corrected, so there is no risk of mistaking the phase shift method due to the influence of noise, and the variable frequency divider Phase adjustment is performed by switching between 31 division and 33 division in 4. In addition, this receiver reads the transmission signal sent in the biphase code by using the signal φc from the decoder 5 to read the first half of the 1-bit period, and by using the signal φa from the decoder 5 to read the second half of the 1-bit period. To do this. FIG. 3 is a block diagram of a different embodiment of a receiver used in the system of the present invention, and the same parts as in FIG. 1 are given the same reference numerals. In this embodiment, there is provided a gate circuit 9 that takes the exclusive OR of the contents of the input stage and output stage of the shift register 3, and the output of this gate circuit 9 is connected to the data terminal D to output Tb of the decoder circuit 5.
A third flip-flop circuit 10 is provided which receives the frequency at its timing terminal T, and the output of the third flip-flop circuit 10 switches whether the amount of change in the frequency division period in the variable frequency divider 4 is increased or decreased. That is, in this embodiment, at the timing when the signal tb is issued from the decoder 5, there is a change point between "H" and "L" of the transmission signal (bit change point) in the shift register 3, and the gate 9 exclusively The third flip-flop circuit 10 has a logical sum.
When the output is set to "H", the frequency division state of the variable frequency divider 4 is "H" or "L" of the signal from the gate 8.
The frequency is switched to 31 division or 33 division depending on the frequency.
On the other hand, at the timing when the signal tb is issued, the transmission signal is "H" in the shift register 3.
When there is no "L" change point (bit change point), exclusive OR is not taken at gate 9, and the output of third flip-flop circuit 10 is set to "L", the variable frequency divider 4 The frequency division state is switched to 29 frequency division or 35 frequency division according to the "H" or "L" level of the signal from gate 8, respectively. The following table shows the outputs of the gate 9 and the third flip-flop circuit 10 at the output timing of the signal tb from the decoder 5, and the switching of the frequency division state.

[Table] In this way, in this embodiment, when the rising timing of tb is close to the bit change point of the transmission signal sent from the transmitting side, the amount of frequency division switching in the variable frequency divider 4 is reduced. There is. G) Effects of the Invention As described above, the clock synchronization system of the present invention detects the direction of phase shift between the output from the majority logic circuit and the clock signal from the clock generation circuit using the phase comparator circuit on the receiver side. As a result, the generation state of the clock signal in the clock generation circuit is changed, so even if the transmission signal contains noise, the phase shift with the clock signal is accurately detected, reliable synchronization is achieved, and the transmission No errors occur in the decoding of data sent on the signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a receiver used in the clock synchronization system of the present invention, FIG. 2 is a timing chart for explaining the operation of this receiver, and FIG. 3 is a diagram of another receiver used in the present invention. FIG. 2 is a block diagram of an embodiment. 1...Shift register, 3...Majority logic circuit, 4...Variable frequency divider circuit, 5...Decoder, 6,
7, 10... flip-flop circuit, 8, 9...
Gate.

Claims (1)

[Claims] 1. In a data transmission system that transmits data using a signal that regularly changes between "H" and "L" levels at a predetermined period, the receiving side has a signal with a period shorter than the changing period of the transmission signal sent from the transmitting side. at least a 3-bit shift register that sequentially takes in the level of the transmission signal according to a basic clock having a basic clock, and extracts the higher level of the "H" or "L" level of the transmission signal taken into the shift register. a majority logic circuit; a frequency divider circuit that divides the basic clock to generate a timing signal corresponding to a changing period of the transmission signal; and a frequency division circuit for the output of the majority logic circuit according to changes in the level of the transmission signal. a phase comparison circuit that detects the phase shift direction of the timing signal from the circuit, and changes the frequency division ratio of the frequency divider circuit according to the phase shift direction comparatively detected by the phase comparison circuit to detect the timing signal. A clock synchronization method characterized by reducing the phase difference with respect to the transmission signal.