JPH0325101B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a synchronization method for a receiver used in digital data transmission.

(b) Conventional technology Conventionally, when synchronizing a digital signal sent from a transmitter and a clock signal of a receiver, the direction of the phase shift between the two signals and the There are methods that detect the size and apply appropriate correction, and methods that detect only the direction of the phase shift and apply a fixed amount of correction in the appropriate direction.

(c) Problems to be solved by the invention However, in the former method of detecting the direction and magnitude of the phase shift and applying appropriate correction, the circuit scale becomes very large and the stability of the oscillation circuit cannot be ensured to a certain extent. In the case of the system with the latter, it is thought that there is no point that is extremely superior to the latter, except for the speed of initial synchronization. In other words, even though the circuit scale is large, great performance cannot be obtained.

On the other hand, in the method of detecting only the direction of phase shift, the circuit configuration is simple, but when considering the stability of synchronization, the amount of correction cannot be made large. For this reason, if there is a large phase shift when the receiver starts receiving signals, there is a problem in that it takes a very long time to achieve initial synchronization, resulting in poor transmission efficiency.

(d) Means for solving the problem The present invention transmits data using codes with a periodic code rule, and the receiving side includes a clock generation circuit and a clock signal from the clock generation circuit. a code violation detection circuit that detects a code violation in a data signal based on a data signal from a transmitting side;
is provided, and when a code violation is detected by the code violation detection circuit at the start of reception, the clock signal generation state of the clock generation circuit is changed.

(E) Operation At the start of reception, when a code violation is detected by the code violation detection circuit, the clock signal generation state of the clock generation circuit is changed, so initial synchronization can be performed without using a new initial synchronization circuit.

(F) Embodiment FIG. 1 is a schematic diagram of the main parts of a receiver used in the clock synchronization system of the present invention, in which 1 indicates data sent using a code with a periodic code rule, for example, a barfase code. A code rule violation detection circuit 2 receives the signal D as a received signal, and 2 is a clock generation circuit that largely changes the generation period of the clock signal by the output from the code rule violation detection circuit 1. is applied to circuit 1. A phase comparison circuit 3 compares the phases of the data signal and the clock signal and finely adjusts the clock synchronization of the clock generation circuit 2 so that these signals are synchronized.

FIG. 2 shows the waveform of the data signal D based on the above-mentioned barphas code. In this barphas code, the signal changes between "H" and "L" at the end of each bit period, and furthermore, the signal level changes in the bit period representing φ. In the center of the bit period where there is no change and represents 1, there is a change in the signal level of "H" and "L". For this reason, normally, the values in the first half of each bit period and the values in the second half are determined by clock _φ1 , which detects the value in the first half of each bit period, and clock _φ2 , which provides the timing to detect the value in the second half of each bit period. A method is used to read data by comparing values.

In such a data transmission system, when data signal D and clock signals φ ₁ and φ ₂ are synchronized as shown in FIG. 3, the detected value of data signal D at φ ₂ and the data signal at the next φ ₁ The detected values of D are always different. On the other hand, when data of all φ is being sent, this data signal D and the clock signal φ ₁ ,
If the phase of φ ₂ is significantly shifted, as shown in Figure 4,
The detected value of the data signal D at the time of _φ2 and the detected value of the data signal D at the next time of _φ1 are the same. In the present invention, synchronization at the initial stage of data signal reception is achieved using this principle.

FIG. 5 is a detailed circuit diagram of FIG. 1, and is constructed to achieve initial synchronization based on the principle described above. Also, in this figure, the same parts as in FIG. 1 are designated by the same reference numerals. In the figure, 4 and 5 are flip-flop circuits that receive the data signal D at the drive terminal D, 6 is a gate that takes the exclusive OR of the Q outputs of these flip-flop circuits 4 and 5, and 7
8 is a flip-flop circuit that receives the output of gate 6 at drive terminal D, and 8 is a variable frequency divider with a built-in basic clock generation circuit. When a signal is given to the CC input terminal, the frequency is divided by 17, and when a signal is given to the CC input terminal, the frequency is divided by 24 regardless of the signals to the CA and CB input terminals. The basic clock used in the variable frequency divider 8 is set so that 16 pulse times approximately correspond to the 1-bit period length of the transmitted data D. Further, the output of the flip-flop circuit 7 is applied to the CC input terminal. A decoder 9 decodes the output of the frequency divider 8, and outputs signals φ ₂ , φ _b , φ ₁ , φ corresponding to output values of 4, 8, 12, and 14, respectively. _a is output, and these φ ₁ , φ ₂ ,
φ _a is applied to the clock terminals (CLK) of flip-flop circuits 5, 4, and 7, respectively. Further, φ ₁ and φ ₂ are used to decode the transmission data signal D consisting of a biphase code. Further, the phase comparison circuit 3 receives the data signal D and the signals φ ₂ and φ _b from the decoder 9, and compares the value of the data signal D at the φ ₂ timing with the value of the data signal D at the φ _b timing to determine whether there is a difference. When the variable frequency divider 8 is
A signal is applied to the CA terminal, and when there is no difference, a signal is applied to the CB terminal of the variable frequency divider 8.

In a circuit having such a configuration, a data signal D representing 0\ is continuously sent at the start of data transmission. At this time, as shown in FIG. 6, the data signal D and the decoding signals φ ₁ and φ ₂ are out of phase,
Assuming that there is a timing φ ₂ in the first half of each bit of the data signal D and a timing φ ₁ in the second half of each bit, the data signal D at the timing φ ₂ detected by the flip-flop circuits 5 and 4 The value of the data signal D at the next timing φ ₁ is equal to the value of the data signal D at the next timing φ 1 , and an “L” signal is applied from the gate 6 to the flip-flop circuit 7 . When the variable frequency divider 8 counts 14, φ _a is applied from the decoder 9 to the clock terminal (CLK) of the flip-flop circuit 7, so that the output of the flip-flop circuit 7 becomes "H" and the output from the variable frequency divider 8 becomes "H".
An “H” signal is applied to the CC input terminal of Correspondingly, this frequency divider 8 enters the frequency dividing state by 24, and the generation of the next φ ₂ is delayed by 1/2 period. This results in
Signals φ ₁ and φ ₂ have timings corresponding to the first and second half of each bit period, respectively. After that, there is a bit edge between φ ₂ and the next φ ₁ , so φ ₂ and this φ ₂
At the next timing φ ₁ , the value of the data signal D changes, and the gate 6 can perform an exclusive OR. Therefore, at the timing of φ _a following φ ₁ above, the output of the flip-flop circuit 7 goes “L”.
Therefore, the frequency-divided output of the variable frequency divider 8 is controlled by the output of the phase comparison circuit 3.

That is, the phase comparator circuit 3 compares the value of the data signal D at the timing of φ ₂ with the value of the data signal D at the timing of φ _b following this φ ₂ , and if these values are equal, the data signal D is On the other hand, it is determined that the clock signals φ ₁ and φ ₂ are slightly ahead, and a signal is applied to the CB input terminal of the variable frequency divider 8, and the variable frequency divider 8 enters the frequency division state by 17, and the clock signals φ ₁ ,
Delay the phase of φ ₂ by 1/16 period. In contrast,
If the value of the data signal D detected at the timing of φ ₂ described above and the timing of φ _b following this φ ₂ are not equal, the clock signals φ ₁ and φ ₂ are slightly delayed with respect to the data signal D. , and a signal is given to the CA input terminal of the variable frequency divider 8. As a result, the variable frequency divider 8 enters a frequency dividing state by 15 and advances the phases of the clock signals φ ₁ and φ ₂ by 1/16 period. That is, in this phase comparison circuit 3, fine adjustment is made by switching the frequency division state of the variable frequency divider 8 so that φ _b is substantially synchronized with the end of each bit period of the data signal D. The operating waveforms of the circuit shown in FIG. 5 are shown in FIG.

Furthermore, during the transmission of the data signal D using the barfaze code, if noise or the like gets on the data signal D and a code rule violation occurs, the output of the flip-flop circuit 7 goes high in the same operation as described above.
A signal is transmitted to a control circuit (not shown) of the receiver to notify that a code rule violation has been detected.

(g) Effects of the invention As stated above, the clock synchronization method of the present invention has the following effects:
Data transmission is performed using codes with a periodic code rule, and the receiving side has a clock generation circuit, and the code in this data signal is determined by the clock signal from this clock generation circuit and the data signal from the transmitting side. A code violation detection circuit is provided to detect a violation, and when a code violation is detected by this code violation detection circuit at the start of reception, the clock signal generation state of the clock generation circuit is changed, so that a new initial synchronization is performed. It is possible to perform rough initial synchronization without installing a circuit, and then move on to fine adjustment of the phase using a phase comparison circuit, which improves initial synchronization compared to conventional methods that only use a phase comparison circuit. This reduces the amount of time required and increases the transmission efficiency of a transmission system using this type of clock synchronization method.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of the main parts of a receiver used in the clock synchronization system of the present invention, FIGS. 2 to 4 are waveform diagrams for explaining the operating principle of the present invention, and FIG. The detailed block circuit diagram, FIG. 6, is an operating waveform diagram of FIG. 5. DESCRIPTION OF SYMBOLS 1... Code rule violation detection circuit, 2... Clock generation circuit, 3... Phase comparison circuit, 4, 5, 6... Flip-flop circuit, 8... Variable frequency divider, 9... Decoder.

Claims (1)

[Claims] 1. In a data transmission system that transmits data using a barphas code having a periodic code rule, the receiving side has a first detection timing that sets the detection timing in the first half and the second half of each bit period of the data signal from the transmitting side. and a clock generation circuit that generates a second clock, and a code violation detection circuit that detects a code violation when the phase relationship between the first and second clock signals is reversed based on a synchronization signal of a constant period, When synchronizing the receiving side with the transmitting side by giving a synchronization signal of a constant period according to the data signal from the transmitting side to the receiving side, when a code violation is detected by the code violation detection circuit, the first and second A clock synchronization method characterized in that the timing of generation of a clock signal is changed by half the cycle of the synchronization signal.