JP2696812B2 - Clock pulse regeneration device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a clock for reproducing a clock pulse from a burst digital signal, in particular, a burst multi-valued digital signal transmitted by being band-limited by a Nyquist filter or the like. The present invention relates to a pulse reproducing device. The (prior art) generally multivalued (e.g., four values) eye pattern signal obtained through the Nyquist filter has a waveform such as of FIG. 5 (a), the result of comparison identifies this waveform at the center voltage V ₀ Is shown in FIG. 5 (b). The interval tau ₁ of FIG. 5 (b) takes a value of either part "1" or "0" of the eye is open, but in the interval tau _2, be a region in which a change in the rise and fall of the waveform It is not easy to obtain phase information from this signal waveform. Conventionally, in order to obtain a clock pulse from an eye pattern in such an information signal, an analog circuit as shown in FIG. 6 is often used. In FIG. 6, the received eye pattern as shown in FIG. 5 (a) is input to INPUT1, and after removing the influence of the low frequency component by the high-pass filter 21, the circuit 22 performs full-wave rectification to obtain the clock frequency component. make. Next, a clock frequency component is extracted by the N-pass filter 23, and quantization noise unique to the N-pass filter is removed by the band limiting filter 24. The output of the filter 24 is compared with a reference voltage V ₁ (the center voltage of the filter 24) by a comparator 25, and is converted into a rectangular wave. The output of the comparator 25 is delayed by a variable delay circuit 26 by an appropriate value. The delay circuit 26 is for adjusting the phase of the reproduced clock so that the received eye can be identified with the optimum phase, but is also used for correcting the variation in the amount of delay generated in the circuits 21 to 24. . (Problems to be Solved by the Invention) This conventional circuit has the following disadvantages. First
Mainly because analog circuits such as filters are used
It is not suitable for IC, and it is not easy to reduce power consumption and downsize. Second, it is necessary to adjust the delay of the reproduced clock pulse with respect to the received eye pattern by the delay circuit 26, which requires an adjustment man-hour and is not economical especially in mass production. (Means for Solving the Problems) A clock pulse reproducing apparatus according to the present invention inputs a burst-like digital signal composed of a multilevel digital information signal and a binary periodic pattern added before the information signal. A clock pulse regenerating device for regenerating a clock pulse in response to the input digital signal, receiving the input digital signal, and determining whether the binary periodic pattern matches a predetermined pattern; A first circuit that outputs a first signal (x1) during a time when it is determined that
When the first signal (x1) is continuously output for the first time (Tm), the second time (Tn ') after the first signal (x1) is no longer output from that point in time. ), A second circuit that outputs a second signal (x3) until the time elapses,
The input digital signal and the second signal (x3) are received, and the second signal (x
3) performing a phase correction at a time when the signal (3) is not output, and stopping the phase correction at a time when the second signal (x3) is output to reproduce the clock pulse. It is characterized by the following. (Example) Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a clock pulse reproducing apparatus according to the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. The received demodulated waveform of FIG. 5 (a) input to INPUT1 is compared with a reference voltage (the above-described center voltage V ₀ ) by the comparator 8 to become a signal of INPUT2. In the section τ ₂ of FIG. 8B, the time point at which the rise and fall change is not determined. However, when a periodic pattern is added before the information signal, the phase of the point where the waveform of INPUT2 changes with respect to the periodic pattern is uniquely determined. That is, in FIG. 2, section τ ₁ is a periodic pattern of “1010...” And section τ ₂ is an information signal. In the method of the present invention, as is apparent from the following description, phase information is obtained only from this periodic pattern "1010 ...". In FIG. 1, a circuit 7 is a clock pulse reproducing circuit that obtains phase information from INPUT 2 and reproduces a clock pulse, and is controlled by a control circuit 6. As shown in FIG. 2, the control circuit 6 measures the time during which the periodic pattern continues, and when it is determined that the periodic pattern continues for a certain time Tm or more, generates a command for fixing the phase of the next Tn time clock. It is. Hereinafter, the operation of the control circuit 6 will be described. The control circuit 6 includes a circuit 1 the received signal to the determining that the periodic pattern output x ₁ "0" of the "1010 ...", the output x ₁ of the circuit 1 is at Tm time "0" state When output x ₂ of the counter 2 to "1", the output x ₂ is "1" and turned to output a "0" on the output x ₃ to section Tn to the end to receive the information signal from the counter 3 It is composed of The output x ₃ = 0 becomes the control signal CONT for fixing the phase to the clock pulse reproducing circuit 7. Circuit 1 has input INPUT2
Is stored in the shift register 4, and the contents of the shift register 4 are input to the memory 5. The memory 5, and outputs "0" into the even output x ₁ when the erroneous bit cyclic pattern A = 10101010 or = 01010101 or A or to otherwise the written value to output "1" I have. Therefore, the transmission path condition is poor, for example, to the reception of the periodic pattern, is corrected in the circuit 1 even when the erroneously 10101110, the output x ₁ it is determined that the cyclic pattern in the received "0 " This type of circuit 5 can be realized by simply using gates such as NAND and NOR. The counter 2 is cleared for x ₁ = 1, counts the clock pulse during x ₁ = 0, starts the output when the time of Tm elapses, and returns to the inhibitor terminal CI to stop counting. Counter 3 is cleared for x ₂ = 1, x ₂ =
The clock pulse is counted during 0, and after the time Tn ', the output rises and returns to the inhibitor terminal CI to stop counting. According to Figure 2, first, when the cyclic pattern is input to the INPUT2, detects this in circuit 1, output x ₁ = 0
To When x ₁ = 0 continues for the time Tm, the output x _{2 of the} counter 2 rises and x ₂ = 1. Next, x ₂ = 0 is reached when it is determined that the signal ₁ is not a periodic signal of “1010...” In the section of the information signal and x ₁ = 1. x ₂ = 1
On the other hand, the output of the counter 3 becomes x ₃ = 0, but it becomes the section of the information signal, and when x ₂ = 0, x ₃ becomes after the time of Tn ′
= 1. Therefore, the output x ₃ is 0 from after cyclic pattern lasted time Tm, which is the time Tn up to several bits went beginning the information signal. The output x ₃ is used as the control signal CONT of the clock pulse regeneration circuit 7. The clock pulse reproducing circuit 7 can be realized by a relatively simple circuit because the bit period of the clock pulse can be obtained only from the periodic pattern input from INPUT2. FIG. 3 shows a specific example of the clock pulse reproducing circuit 7. In FIG. 3, reference numeral 20 denotes an oscillation circuit using a crystal and having a frequency f ₀ , and reference numerals 17, 18 and 19 denote frequency dividers.
_{1 = f 0 / k 1,} f 2 = f 0 / k 2, f 3 = outputs a pulse train of frequency f ₀ / k _3. Here, a set to have a relation of _{f 1 <f 2 <f 3} . The outputs of dividers 17 and 18 are connected to switch 9
The outputs of the divider 18 and the switch 9 are connected to the switch 10. Further, the output of the switch 10 is connected to the frequency divider 11. The division number k ₄ of the divider 11 and the division number k _{2 of the} divider 18 give f ₂
/ (K ₂ k ₄ ) = f _CLK (clock frequency). k ₄ is a sufficiently large value, and switches 9 and
The output y ₁ is selected so that the phase of CLKOUT can be regarded as a continuous change even for the 10 switching operations. The circuit 16 generates the recovered clock pulse y ₁ = CLKOUT and the input y
₀ is a circuit for detecting the phase lead or lag of the (INPUT2 of FIG. 1) to select one of f ₁ and f ₃ are inputted to the switch 9 by the output of the circuit 16. The phase of the y ₁ compared to y ₀ is delayed in this case, choosing f _3. The switch 10 switches whether to fix the phase. That is, the control signal CONT (output of the counter 3 of FIG. 1) becomes "0" (i.e., the instruction is added to the fixed phase), f ₂ is selected. FIGS. 4 (a) and 4 (b) show time charts of the circuit 16.
In each case, a periodic pattern is input to y ₀ = INPUT2, and (a) shows a reproduced clock pulse y ₁ = CLKO
(B) shows a case where the reproduced clock pulse y ₁ = CLKOUT is advanced when the phase of the UT is delayed. Creating an inverted signal y ₂ of y ₁ by the inverter 12 of FIG. 3, to extract the waveform of y ₀ with respect to the rise of the signal y ₂ by the flip-flop 13. The resulting y ₃ exclusive input y ₀ OR circuit 14
, And the output y ₄ is input to y ₁ and the flip-flop circuit 15 for phase comparison. Result of extracting y ₄ with y ₁ y ₅
If but one, who y ₁ is the phase lag than y _0, if y ₅ is 0, those of y ₁ means a phase advance than y _0. When the control signal CONT is 1, i.e., when no information signal section, since the output of the switch 9 is input to the 11, and one of f ₁ or f ₃ is selected for the input y _0, the output y ₁ follows the phase. For example, when the direction of y ₁ is delayed from y _0, as in the 4 (a), the output y ₅ of the circuit 16 becomes 1, is f ₃ are selected, f to only slightly higher frequency than the data rate since _CLK is set, y ₁ will catch up to y _0. When the control signal CONT is 0, i.e., at the information signal section, y ₁ is selected to the frequency _{f CLK = f 0 / (k} 2 k 4) of the fixed phase. Thus, for example, in the information signal section is 1000 symbols, and the symbol rate f _s of the received data, if the frequency difference f _CLK is 5 × 10 ^-8, during which the deviation is, 360 × 1000 ×
5 × 10 ⁻⁸ = 1.8 deg, and there is no practical problem. Here, the clock pulse reproducing circuit shown in FIG. 3 has been described as a specific example, but a clock pulse is reproduced from a periodic pattern of “1010...” And the phase of the reproduced clock pulse can be controlled to be fixed. Other clock pulse regeneration circuits can also be used. In the present invention, as shown in FIG. 3, a circuit for reproducing a clock pulse only from a periodic pattern of a received signal is sufficient, and it can be realized relatively easily using a digital circuit. In realizing the present invention, the control circuit 6 shown in FIG. 1 and the clock pulse regeneration circuit shown in FIG. 3 can all be realized as a one-chip IC using a gate array. (Effects of the Invention) As described above, since the clock pulse reproducing device of the present invention can be implemented entirely by digital circuits, it is suitable for IC integration, and low power consumption and small size are easy. Moreover,
The phase plane of the reproduced clock pulse is set in a range where there is no problem in practical use, there is no element that causes variation depending on the circuit, and no adjustment is required. Therefore, the method of the present invention has advantages such as economy at the time of mass production.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a clock pulse reproducing apparatus according to the present invention, FIG. 2 is a time chart of signals of respective parts of the embodiment of FIG. 1, and FIG. FIG. 4 is a block diagram showing a specific example of the clock pulse reproducing circuit 7 in the embodiment. FIGS. 4 (a) and (b) are time charts of signals of respective parts in the specific example of FIG. 3, and FIGS. Is a diagram showing an example of an eye pattern of an information signal used in the present invention, and FIG. 6 is a block diagram showing a conventional clock pulse reproducing device.

Claims (1)

(57) [Claims] A clock pulse reproducing device which inputs a burst-like digital signal composed of a multilevel digital information signal and a binary periodic pattern added before the information signal and reproduces a clock pulse in response to the input digital signal. Receiving the input digital signal, determining whether the binary periodic pattern matches a predetermined pattern, and outputting a first signal (x1) during a time when it is determined that the binary periodic pattern matches the predetermined pattern; A first circuit, when the first signal (x1) is output continuously for a first time (Tm), from that point on, after the first signal (x1) is no longer output, A second circuit for outputting a second signal (x3) during a time period until the second time (Tn ′) elapses, receiving the input digital signal and the second signal (x3), and receiving the input digital signal. With respect to the second signal (x
3) performing a phase correction at a time when the signal (3) is not output, and stopping the phase correction at a time when the second signal (x3) is output to reproduce the clock pulse. A clock pulse reproducing device characterized by the above-mentioned.