JPH01180118A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To quicken the pull in time and to suppress the period fluctuation of an output signal by using a mask signal to apply phase locking and providing a blind sector to a phase comparator. CONSTITUTION:An input signal and a mask signal are given to a mask decision circuit 4, the circuit 4 decides the relation of phase of both the input signals, and when the input signal is within the mask signal, an input signal in the mask is outputted and when the input signal is at the outside of the mask signal, the input signal at the outside of the mask is sent. The input signal within the mask is given to a phase comparator 1 and the input signal at the outside of mask is given to a variable period counter 2. A frequency division counter of a counter 2 is reset forcibly and starts counting in the same phase as that of the input signal. Thus, the input signal and the output signal reach the same phase at the next period and the phase locking is finished. On the other hand, the comparator 1 compares the phase of the input signal within mask with the phase of the output signal, and when the phase difference exceeds a prescribed value, a lead or lag signal is outputted. When the phase difference is within the dead band, the output signal is fixed to the reference period.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Use) The present invention relates to a digital PLL circuit that performs phase synchronization in digital transmission.

[Conventional technology]

FIG. 5 shows a conventional digital PLL circuit as shown in, for example, Japanese Patent Publication No. 61-44423. (2) is the phase comparator that generates this lead/
A variable period counter changes the phase of an output signal according to a delay signal, and (3) is a constant frequency oscillator that drives this variable period counter.

A conventional digital PLL circuit is configured as described above,
The phase comparator (1) periodically compares the phases of an input signal and an output signal, and generates a lead signal or a delay signal depending on the phase relationship. For example, if the output signal is ahead of the input signal, a lead signal is generated, and if the output signal is behind the input signal, a delay signal is generated, and these signals are sent out. When the variable cycle counter (2) receives the advance signal, it lengthens the cycle of the output signal (T-T) as shown in Figure N6 (a).
+ΔT) If the phase is delayed and a delayed signal is received,
As shown in FIG. 6(b), the period of the output signal is shortened (T-T-ΔT) to advance the phase. As a result, an output signal synchronized with the phase of the input signal is generated.

(Problems to be Solved by the Invention) In the conventional digital PLL circuit as described above, when the input signal and the output signal are largely out of phase, it takes time to achieve phase synchronization, and ,
Unless the phases of the input signal and the output signal completely match, phase adjustment is always performed, which causes problems such as fluctuations in the period of the output signal.

The present invention was made to solve this problem, and an object of the present invention is to provide a digital PLL circuit that can speed up the initial phase pull-in and suppress fluctuations in the period of the output signal after the pull-in. shall be.

(Means for Solving the Problems) A digital PLL circuit according to the present invention includes a mask generation circuit that generates a mask signal having a certain time width based on an output signal, and a mask generation circuit that determines whether or not an input signal is within the mask signal. The mask judgment circuit that makes the judgment compares the phases of the input signal and output signal within the mask signal, and proceeds when the phase difference exceeds a certain value.

a phase comparator that outputs one of the delayed signals; a variable period counter that is reset based on an input signal other than the mask signal and adjusts the phase of the output signal by the output signal from the phase comparator; A driving oscillator with a constant frequency is provided.

(Operation) In this invention, the input signal (
A non-mask input signal (hereinafter referred to as a non-mask input signal) is directly applied to the variable period counter from the mask determination circuit, and is forcibly synchronized. For this reason, it becomes possible to quickly perform the initial phase pull-in.

The phase comparator also detects the input signal (
Phase comparison is performed on the input signals (hereinafter referred to as input signals in the mask), and only when there is a phase difference exceeding a certain value, a lead signal or a delay signal is sent out to adjust the phase of the variable period counter. It is possible to suppress fluctuations in the period of the output signal after the pull-in.

(Embodiment) FIG. 1 shows an embodiment of the present invention.
) is a mask judgment circuit that judges the phase relationship between the input signal and the mask signal, and (1) compares the phase of the input signal in the mask and the output signal, and when the phase difference exceeds a certain value, an advanced signal is output. Or a phase comparator that outputs a delayed signal (2
) is a variable period counter that is forcibly reset by an input signal outside the mask and adjusts the phase of the output signal by a lead signal or a delay signal, and (3) is this variable period counter (2).
(5) is a mask generation circuit that generates a mask signal having a constant time width based on the output signal.

FIG. 2 shows details of the variable period kakunta (2). In the figure, (6) is a frequency division counter, and (7) is a counter carry from this frequency division counter (6) that is delayed and A shift register that generates a periodic signal (T), a shorter period signal (T-ΔT), and a longer period signal (T+ΔT), (8) selects one signal from these three signals. The selector (9) used as an output signal is an up/down counter that controls the selection code of this selector (8).

In the digital PLL circuit configured as described above, the input signal and the mask signal are sent to the mask judgment circuit (4).
is input. The mask determination circuit (4) determines the phase relationship between the input signal and the mask signal, and when the input signal falls within the mask signal, sends out the input signal within the mask as shown in FIG. 3(a). However, if the input signal is outside the mask signal, the outside mask input signal is sent out as shown in FIG. 3(b).

As shown in FIG. 1, the in-mask input signal is applied to a phase comparator (1), and the out-mask input signal is applied to a variable period counter (2).

The frequency division counter (6) of the variable period counter (2) is forcibly reset by the input of the non-mask input signal, and starts counting at the same phase as the input signal. Therefore, in the next cycle, the input signal and the output signal are almost in phase, and the synchronization pull-in is completed.

On the other hand, the phase comparator (1) receives the input signal in the mask and compares the phase of the input signal in the mask and the output signal, and outputs a lead signal or a delay signal only when the phase difference exceeds a certain value. do. That is, the phase comparator (1) is provided with a certain dead zone. Figure 4 (a) is a time chart when the phase difference is within the dead zone and no phase control signal is generated, Figure 4 (b) is a time chart when a leading signal is generated, and Figure 4 (c) is a delayed signal. The time charts for generating each are shown below.

The selector (8) of the variable period counter (2) outputs a long period (T+ΔT) output for a leading signal, a short period (T-ΔT) output for a delayed signal, and selects which signal. If the reference period (T) does not come, the output of the reference period (T) is selected and used as the output signal. Thereby, the phase of the output signal is adjusted to follow the input signal, and if the phase difference is within the dead zone, no phase adjustment is performed and the output signal is fixed to the reference period. Therefore, frequent phase fluctuations in the output signal due to changes in the input signal can be avoided.

In the above embodiment, the variable period counter (2) is immediately reset by one non-mask input signal, but it may be reset after the non-mask input signal is generated several times. .

〔Effect of the invention〕

As explained above, this invention performs phase synchronization using a mask signal, so it is possible to speed up the synchronization pull-in time, and since a dead zone is provided in the phase comparator, the period of the output signal is This has the effect of suppressing fluctuations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital PLL circuit showing an embodiment of the present invention, FIG. 2 is a block diagram showing details of the variable period counter of FIG. 1, and FIGS. 3(a) and (b) are diagrams of the present invention. FIG. 4(a) is a time chart showing the operation of the mask determination circuit in FIG. (b) and (c) are time charts showing the phase control in this invention, and FIG.
A diagram equivalent to Figure 1 showing the LL circuit, Figure 6 (a), (b
) are time charts showing phase control in a conventional digital PLL circuit. (1)... Phase comparator, (2)... Variable period counter, (3)... Oscillator, (4)... Mask determination circuit, (5)... Mask generation circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A mask generation circuit that generates a mask signal having a fixed time width based on an output signal, a mask determination circuit that determines whether an input signal is within the mask signal, and a mask determination circuit that determines whether the input signal is within the mask signal and the output signal is within the mask signal. A phase comparator that compares the phases and outputs either an advanced or delayed signal when the phase difference exceeds a certain value, and a phase comparator that is reset based on an input signal other than the mask signal and output by the output signal from the phase comparator. A digital PLL circuit comprising: a variable period counter that adjusts the phase of a signal; and a constant frequency oscillator that drives the variable period counter.