JPS61163411A - Traveling adjusting control circuit - Google Patents

Abstract

PURPOSE:To synchronize and follow in a wide range and to output a stable traveling adjusting synchronization clock by inputting an external reference clock, taking a synchronization by a phase locked loop,and dividing a synchronization clock thereof by a variable frequency divider to obtain the traveling adjusting synchronization clock. CONSTITUTION:An external reference clock is given to a phase detector 4 from an external reference clock input terminal 2 and constitutes a phase synchronization loop together with a voltage control crystal oscillator 5 to obtain a crystal originated oscillating master clock 10. A frequency comparator 7 inputs an external traveling adjusting signal from the master clock and an external traveling adjusting signal input terminal 1 and a frequency thereof is outputted to a variable divider 6 as a dividing ratio setting signal 9. The variable divider 6 inputs the master clock 10 and it is divided by the dividing ratio indicated by the dividing ratio setting signal 9 and outputted to a traveling adjusting synchronization clock output terminal 3. In such a manner, the traveling adjusting synchronization clock having the wide range of a following characteristic and the high accuracy can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a start-up control circuit in, for example, a digital recording/playback device.

[Conventional technology]

! FIG. 3 shows a configuration example of a conventional start-up control circuit, which is well known as a phase locked loop (Pbase LockTAop). In the s3 diagram, (1
) is an external start-up signal input switch, (31 is a start-up synchronization clock output switch, (4: is a phase detector, - is a voltage-controlled oscillator).

(8) is the error voltage.

Next, I will explain #work. The external tuning signal is given to the phase detector (41) from the force sensor (1).The phase detector detects the error between the external tuning signal and the clock output from the voltage i1tIILm oscillator, and outputs the error voltage (8 ) as a voltage-controlled oscillator (provided.The voltage-controlled oscillator U outputs the lock to the phase detector and the synchronized clock output terminal (3) Gζ so that the error is minimized.In this way, this system constitutes a feedback loop. The external start-up signal and the start-up synchronization clock are balanced at the point where they coincide, and the start-up synchronization clock is synchronized with the external S start-up signal.

[Problems that the invention attempts to resolve]

Conventional synchronization control circuits are configured as described above, so if the synchronization tracking range is wide, it will be susceptible to input signal jitter and input noise, and the stability of the synchronization clock will deteriorate. For example, when used as a timing pulse inside a digital recording/playback device, there is a problem of deterioration in sound quality, and conversely, if a crystal oscillator or the like is used as a voltage-controlled oscillator to improve stability, the tracking range becomes narrower. There was a point.

In addition, when controlling the internal circuit with a synchronized clock,
Since the synchronization process of this synchronization control circuit with respect to the external synchronization signal is step-like, the internal mechanism
Not only is it not possible to follow the changes (but there is no consideration given to the case where the external start-up signal exceeds the synchronization follow-up range, and in this case,
There were problems such as the inability to keep pace with outsiders.

This invention was made to solve the above-mentioned problems, and has the following objects. Namely.

+11 External tracking signal is synchronized and followed over a wide range,
To obtain a start-up control circuit that outputs a stable start-up synchronous clock with less jitter, residual AM, and residual @FM. In addition to outputting the frequency change speed at a rate of change ζ that the internal mechanism can follow, even if the external start-up signal exceeds the tracking range of the synchronous circuit, an appropriate start-up signal is output to keep the internal mechanism in check. To obtain a racing control circuit that performs racing control.

[Means for solving problems]

The start-up control circuit according to the present invention inputs a highly stable external reference clock from the outside, synchronizes it with a phase-locked loop using a voltage-controlled crystal oscillator, and makes the synchronized clock variable using a variable frequency divider. The frequency is divided to obtain a synchronized clock synchronized with an external synchronization signal.

In addition, the frequency division ratio of the variable frequency divider is changed to 1 when the frequency division ratio changes so that the frequency divider output change can be followed by the internal mechanism.
In Japan, it is divided into membranes to gradually change the frequency to reduce the speed of frequency change, and when the external start-up signal exceeds the synchronous follow-up range, the external start-up signal is output as the internal start-up control signal for that time. This is what I did.

[Effect]

In the present invention, the crystal master clock synchronized with the external reference clock is divided by the variable frequency divider so that the divided output clock is synchronized with the external synchronization signal, and outputted as the synchronization clock.

In addition, the rate of change of the output clock of this variable frequency divider is converted to a rate of change that can be followed by the internal mechanism by controlling the rate of change of the division ratio of the variable frequency divider, and the external tracking signal can be synchronously followed. By using an external start-up signal even when the range is exceeded, it is possible to at least start the internal mechanism even if complete synchronization cannot be achieved.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is an external start-up signal input terminal.

(2) is an external reference clock input terminal, (31 is a synchronized clock output terminal, (41 is a phase detector, (51 is a voltage controlled crystal oscillator, (6) is a variable frequency divider, (7) is a frequency comparison vessel.

(81 is the error voltage, (91 is the division ratio setting signal, ((1)
is the mask clock output by the 1-dominance-crystal I@oscillator.

Next, the operation of the configuration shown in FIG. 1 will be explained. The external reference clock is given to the phase detector (4) from the input terminal (2), and forms a phase-locked loop with the voltage-controlled crystal oscillator (61), which generates a mask of the crystal master oscillator synchronized with the external reference clock.
Get the clock screaming. The frequency comparator (7) inputs the mask clock and the external start-up signal from the input terminal +11, and outputs the frequency difference therebetween to the variable frequency divider (6) as the frequency division ratio &'M signal (91). The frequency unit 1611fi inputs the master clock 0 (1), divides it by the frequency division ratio indicated by the frequency division ratio setting signal (91), and outputs it to the synchronized clock output terminal (3).

FIG. 2 shows another embodiment of this invention, (1
) to shout are the same as in Fig. 1, (b) is the internal start control signal output terminal, (2) is the mute signal output terminal, b is the selector 1 μm 1 selection signal that selects and outputs the input signal, and the light is This is a start-up synchronized clock, and the difference from the one shown in FIG. 1 is that a selector port is added.

In Figure 2, the frequency comparator (7; receives the master clock tl [1] and an external tuning signal from the input terminal (11), and calculates the frequency division ratio of the variable frequency divider (6: It is determined whether or not it is within the branching possible range of the device (6), that is, whether the tracking signal synchronization circuit section is within the tracking possible range, and the result is output to the selector (to) as the selection signal α◆.Following When it is within the possible range, the frequency comparator (7IIf
i. So that the rate of change of the synchronized clock output from the variable frequency divider (6) can be followed by the internal mechanism.
Frequency division ratio setting signal (91 changes are divided into steps,
The change is delayed in time and output to the variable frequency divider. At this time, the selector selects the start-up synchronization clock based on the selection signal and outputs it to the internal start-up control signal output terminal (6).

On the other hand, when the external start-up signal exceeds the synchronization tracking range, the selector selects the external start-up signal +11 according to the selection signal and outputs it to the internal start-up control signal output terminal 4, and at the same time, the frequency comparator outputs a silent signal (miniature control signal). - Tiffugu) output the instruction signal to mute signal output terminal 4.

In the above embodiment, the mute signal is collected as a separate signal, but the selection signal may be used as the mute signal.

In addition, the setting of the frequency division ratio of the variable frequency divider (61) in the 1-frequency comparator (7), the judgment for sending out the selection signal (b) and the mute signal, etc. are controlled by software using a microcomputer, etc. Good too.

〔Effect of the invention〕

As described above, according to the present invention, the synchronization circuit with the external synchronization signal is configured by controlling the frequency division ratio of the crystal master clock. Jitter and residual AM.

It is possible to obtain an M-running synchronized clock (with less residual IPM components), and by using this clock as a timing pulse for a digital high-quality sound reproduction device, etc., there is an effect that deterioration in sound quality (sound vibration, etc.) can be reduced.

In addition, when the external start-up signal is within the synchronization tracking range of the start-up control circuit and when it is not, in the former case, internal start-up control is performed using a start-up synchronization clock having a change rate that can be followed by the internal mechanism. In the latter case, since the system is configured to perform internal start control using an external start signal, it is possible to reproduce high-quality sound without fluctuations, and the internal S* structure can be externally started over a wide range.

[Brief explanation of the drawing]

FIG. 1 shows a start-up control circuit according to an embodiment of the present invention;
The figure shows another embodiment of the present invention; the first and third starting control circuits;
The figure is a circuit configuration diagram of a conventional start-up control circuit. In the figure, (11 is an external control signal input terminal, (2) is an external reference clock input terminal, (3) is a control synchronization clock output terminal, (41 is a phase detector, (41 is a phase detector, (41 is a voltage controlled crystal oscillator, 6) is a variable frequency divider, (7) is a frequency comparator, (b)
(6) is an internal start-up control signal output terminal, (6) is a mute signal output terminal, and - is a selector. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1

Claims (2)

[Claims] (1) A phase-locked circuit that outputs a master clock that is phase-synchronized with an external reference clock; detects the frequency difference between the master clock output from this phase-locked circuit and the input external control signal; and a variable frequency divider that divides the frequency of the master clock according to the frequency division ratio setting signal outputted from the frequency comparator and outputs a synchronized clock. Start-up control circuit. (2) Divide the frequency division ratio of the variable frequency divider into multiple steps to convert the frequency change speed of the synchronized clock to a speed of change that allows the synchronization clock, and also allow the external synchronization signal to control the tracking range of the synchronization circuit. 2. The start-up control circuit according to claim 1, wherein when the start-up timing exceeds the start-up synchronization clock, direct start-up control is performed using an external start-up signal instead of the start-up synchronization clock.