JPS6014522A - Generator for clock signal synchronized with digital signal - Google Patents
Generator for clock signal synchronized with digital signalInfo
- Publication number
- JPS6014522A JPS6014522A JP58122603A JP12260383A JPS6014522A JP S6014522 A JPS6014522 A JP S6014522A JP 58122603 A JP58122603 A JP 58122603A JP 12260383 A JP12260383 A JP 12260383A JP S6014522 A JPS6014522 A JP S6014522A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- clock signal
- synchronized
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised Effects 0.000 title abstract 5
- 238000001514 detection method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
Abstract
PURPOSE:To obtain a stable clock signal in a capture range by dividing the frequency of the output of a variable frequency oscillating circuit by N to generate a reference frequency approximating 1/N of the bit frequency of an input signal and detecting a phase difference between both signals and controlling said oscillating circuit by the detection output. CONSTITUTION:If it is detected that a clock signal is not synchronized with a digital signal A to close a switch 6, the phase of an output frequency-divided clock signal E of a frequency divider 3 and that of a reference clock signal F are compared with each other. At this time, frequencies fE and fF are 1/N of fc and fb, and the frequency diference and the phase difference between fc and fb are 1/N, and the signal E is synchronized with the signal F even in case of a slight deviation between fc and fb because signals E and F are inverted at intervals of a half period. Consequently, a clock signal c is synchronized with the digital signal A easily when the switch 6 is opened. Thus, an integer N and the frequency fF are so selected that N.fFapprox.=fb is true, and a phase difference G between signals F and E is applied to an oscillating circuit 2 to synchronize them, and thereafter, the signal C is synchronized with the signal A. An LPF7 raises the gain of a phase synchronizing loop to extend the capture range.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58122603A JPS6014522A (en) | 1983-07-06 | 1983-07-06 | Generator for clock signal synchronized with digital signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58122603A JPS6014522A (en) | 1983-07-06 | 1983-07-06 | Generator for clock signal synchronized with digital signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6014522A true JPS6014522A (en) | 1985-01-25 |
Family
ID=14840023
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58122603A Pending JPS6014522A (en) | 1983-07-06 | 1983-07-06 | Generator for clock signal synchronized with digital signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6014522A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0239623A (en) * | 1988-07-28 | 1990-02-08 | Nec Corp | Pll circuit |
JPH02127817A (en) * | 1988-11-07 | 1990-05-16 | Nec Corp | Phase locked loop oscillator |
JPH0440117A (en) * | 1990-06-06 | 1992-02-10 | Fujitsu Ltd | Pll circuit |
US5097219A (en) * | 1988-12-15 | 1992-03-17 | Mitsubishi Denki Kabushiki Kaisha | Pll for controlling frequency deviation of a variable frequency oscillator |
JPH05129942A (en) * | 1991-11-08 | 1993-05-25 | Matsushita Electric Ind Co Ltd | Pll circuit |
US5384291A (en) * | 1993-06-25 | 1995-01-24 | The Dow Chemical Company | Carbothermal synthesis precursors |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57106241A (en) * | 1980-10-31 | 1982-07-02 | Westinghouse Electric Corp | Phase lock loop |
-
1983
- 1983-07-06 JP JP58122603A patent/JPS6014522A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57106241A (en) * | 1980-10-31 | 1982-07-02 | Westinghouse Electric Corp | Phase lock loop |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0239623A (en) * | 1988-07-28 | 1990-02-08 | Nec Corp | Pll circuit |
JPH02127817A (en) * | 1988-11-07 | 1990-05-16 | Nec Corp | Phase locked loop oscillator |
US5097219A (en) * | 1988-12-15 | 1992-03-17 | Mitsubishi Denki Kabushiki Kaisha | Pll for controlling frequency deviation of a variable frequency oscillator |
JPH0440117A (en) * | 1990-06-06 | 1992-02-10 | Fujitsu Ltd | Pll circuit |
JPH05129942A (en) * | 1991-11-08 | 1993-05-25 | Matsushita Electric Ind Co Ltd | Pll circuit |
US5384291A (en) * | 1993-06-25 | 1995-01-24 | The Dow Chemical Company | Carbothermal synthesis precursors |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0218406A3 (en) | Sampling clock generation circuit | |
CA2152180A1 (en) | Phase locked loop synchronization circuit and method | |
EP0147897A3 (en) | Phase-locked loop capable of generating a plurality of stable frequency signals | |
JPH0292021A (en) | Digital pll circuit | |
JPS6014522A (en) | Generator for clock signal synchronized with digital signal | |
CA2192881A1 (en) | PLL Circuit and Noise Reduction Means for PLL Circuit | |
JPS5357914A (en) | Synchronous oscillator | |
JPS6059822A (en) | Frequency converting circuit | |
JPS59202736A (en) | Phase locked loop circuit | |
JPS6412691A (en) | Video signal sampling circuit | |
JPS6297428A (en) | Pll circuit | |
JPS6413833A (en) | Frame synchronizing clock generating circuit | |
JPS5620355A (en) | Clock signal forming circuit | |
JPS63269827A (en) | Digital pll | |
JPS57162841A (en) | Digital pll circuit system | |
JPS5333038A (en) | Phase synchronizing oscillator | |
FR2336003A1 (en) | Phase control loop for oscillator - is used as phase shifter for generation of phase shift between oscillator and other frequency | |
JPH04326867A (en) | Phase-locked loop | |
JPS57183132A (en) | Phase synchromizing circuit | |
JPS6074728A (en) | Channel setting system of pll synthesizer circuit | |
JPH0191532A (en) | Phase locked loop circuit | |
JPH03242088A (en) | Synchronizing circuit | |
JPS60145727A (en) | Phase locked loop device | |
JPS6027243A (en) | Clock synchronizing system | |
JPS57173267A (en) | Afc circuit |