JPS63299613A - Digital phase locked loop circuit - Google Patents

Abstract

PURPOSE:To generate an extracting clock having an optimum jitter quantity and a jitter frequency compared with the conventional one by adding a loop filter step number setting circuit to a conventional circuit. CONSTITUTION:A phase change decoding part 71 of a filter step number setting circuit 7 receives a presetting signal (d) from a filter 4 and outputs a phase nominal instructing signal d0, a phase lag instructing signal d1 and a phase lead instructing signal d2. For example, when the signal d2 is outputted two times, a counter 72 is set, the setting signal sets an F/F 74 and outputs a continuous phase changing instruction detecting signal d3. A filter step number setting control part 75 sets initially the number of the steps of the filter 4 at the time of turning on the power supply, executes automatically the synchronizing training within a prescribed time, sets the number of steps to +1 and executes the detection of the continuous phase changing signal d3. According to the presence or absence of the signal d3, a step number setting signal (g) to set the number of steps to -1 or +1 from the present condition is outputted. Consequently, the number of the steps is automatically set so that the phase lead or lag of continuous three times or above cannot be executed to an input signal jitter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital phase-locked circuit, and more particularly to a digital phase-locked circuit having a loop filter for generating an extracted clock phase-synchronized with a human input signal.

[Conventional technology]

Conventionally, this type of digital phase locked circuit uses a loop filter in which the number of loop filter stages is fixed.

FIG. 4 is a block diagram showing an example of a conventional digital phase synchronization circuit.

In FIG. 4, the conventional digital phase synchronization circuit has an input signal a and an extracted clock b whose phase is synchronized with this input signal a.
a phase comparator 3 that performs a phase comparison with the input signal a, a change point detection circuit 2 that detects a change point at the rising edge of the input signal a, and counts the number of phase lead signals or phase delay signals output from the phase comparator 3. However, when the number of loop filter stages is continuously counted beyond a predetermined number of loop filter stages, the loop filter 4 increases or decreases the preset value from the nominal value and outputs a preset signal d instructing a phase change, and outputs the original oscillation clock C. It comprises an oscillation circuit 5 and a preset counter 6 which uses the original oscillation clock C as an input clock and generates an extracted clock b by inputting the preset signal d of the loop filter 4.

FIG. 5 is a timing diagram showing the operation of main signals when the number of loop filter stages of the conventional digital phase locked loop circuit shown in FIG. 4 is one.

Next, the operation of the conventional digital phase synchronized circuit will be explained.

4 and 5, the change point of the input signal a is detected by the change point detection circuit 2 at the rising edge of the input signal a, and the change point detection circuit 2 outputs the signal e, and the change point from the preset counter 6 is detected. The phase comparator 3 which compares the phases of the extracted clock b and the input signal a outputs a signal f indicating whether the input signal a is ahead or behind the extracted clock b in phase, and the loop filter 4 outputs a signal f indicating whether the input signal a is ahead or behind the extracted clock b. The number of phase leads or phase lags is calculated, and since the number of loop filter stages of the loop filter 4 is 1, when two or more consecutive phase leads or phase lags are detected, the loop filter 4 uses a preset counter 6 to generate an extraction clock b. Outputs a preset signal d that instructs a phase change of phase lag or phase lead to change the phase of extraction clock b to lag or lead, and sets the period of extraction clock b to the nominal frequency in other cases. do. The preset counter 6 counts the measurement of the input original oscillation clock C from the preset value of the preset signal d, and outputs the extracted clock b.

[Problem that the invention seeks to solve]

In the conventional digital phase-locked circuit described above, the number of stages of the loop filter is fixed in advance, so if the jitter of the input signal changes dynamically over time depending on the line condition or the condition of the other device, the jitter of the input signal will be smaller than the jitter of the input signal, for example. If the number of loop filter stages is small, the sensitivity of the digital phase-locked circuit becomes excessive and the extracted clock jitter frequency becomes high, and if the number of loop filter stages is large relative to the input signal jitter, the sensitivity of the digital phase-locked circuit becomes excessive. A problem arises in that the sensitivity becomes too low and the amount of extracted clock jitter increases.

[Means for solving problems]

The digital phase synchronized circuit of the present invention includes a phase comparator that performs a phase comparison between an input signal and an extracted clock whose phase is synchronized with the input signal, and a change point detection circuit that detects a change point at the rising edge of the input signal. , the number of phase lead signals or phase delay signals of the output of the phase comparator at the change point of the input signal is counted, and when the number is continuously counted beyond a predetermined number of loop filter stages, the preset value is changed to a nominal value. a loop filter that outputs a phase change instruction signal that increases or decreases; an oscillation circuit that outputs an original oscillation clock of the extracted clock; and an oscillation circuit that outputs the original oscillation clock of the extracted clock, and uses the original oscillation clock as an input clock and the phase change instruction signal as a preset input signal to generate the extracted clock. In a digital phase synchronized circuit comprising a preset counter that generates a preset counter, the number of stages of the loop filter is automatically set so that the phase change instruction signal of the loop filter does not instruct three or more consecutive phase advances or lags. It has a loop filter stage number setting circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing an example of the filter stage number setting circuit shown in Fig. 1, and Fig. 3 is a block diagram showing the filter stage number shown in Fig. 2. 3 is a flowchart illustrating an example of a program operation of a setting control section.

In FIG. 1, the digital phase-locked circuit of this embodiment is as follows:
A conventional digital phase-locked circuit shown in FIG. 5 receives a preset signal d from a loop filter 4 and outputs a filter stage number setting signal g whose signal content is the set value of the number of loop filter stages to the loop filter 4. The configuration includes a setting circuit 7.

In FIG. 2, a filter stage number setting circuit 7 receives a preset signal d from a loop filter 4, decodes a phase change instruction, and outputs a phase nominal instruction signal 4 a phase delay instruction signal dl.
A phase change instruction decoder 71 that outputs a two-phase advance instruction signal d8, a phase advance instruction signal counter 72 that counts the number of phase advance instruction signals d2, and a phase delay instruction signal d! When the respective input signals of the phase delay instruction signal counter 73, the phase advance instruction signal counter 72, and the phase delay instruction signal counter 73 are inputted twice in succession, it is detected and a continuous phase change instruction is issued. A continuous phase change instruction detection flip-flop 74 outputs a detection signal d3, and a loop filter 4 receives the continuous phase change instruction detection signal d3.
and a filter stage number setting control section 75 that outputs a filter stage number setting signal g for setting the optimum number of loop filter stages.

The filter stage number setting control unit 75 includes a timer (not shown), a ROM (not shown), etc., and performs sequence control of the entire filter stage number setting circuit 7 using a program stored in the ROM.

Next, the operation of this embodiment will be explained, particularly only the parts that differ from the operation of the conventional digital phase synchronized circuit shown in FIG. 5.

In FIG. 2, a preset signal d from the loop filter 4 is decoded by a phase change instruction decoding section 71, and for example,
When the phase advance instruction signal d is output twice, the phase advance instruction signal counter 72 is set, and the set signal causes the continuous phase change instruction flip 70 knob 74 to be set to output the continuous phase change instruction detection signal d3. .

On the other hand, the filter stage number setting control unit 75 initializes the loop filter stage number of the loop filter 4 according to the program shown in FIG. 3 at the time the power is turned on, and then
A built-in synchronous training timer (not shown) automatically performs synchronous training within a predetermined time, and after clearing the synchronous training timer, the number of loop filter stages to the loop filter 4 is set to +1, and the monitoring timer (not shown) is set to +1. ) is turned on, and the continuous phase change instruction detection signal d is detected.

If there is a continuous phase change instruction detection signal d, a filter stage number setting signal g is output that sets the loop filter stage number to -1 from the current number.

In this way, the filter stage number setting control unit 75 detects the presence or absence of the continuous phase change instruction detection signal d3 within the time preset in the monitoring timer, and detects the presence or absence of the continuous phase change instruction detection signal d3.
If 3 is present, the number of loop filter stages is set to -IK: from the current state, and if not, a filter stage number setting signal g is sent to the loop filter 4, which sets the number of loop filter stages to +IK- from the current state.
Automatically set the number of loop filter stages.

〔Effect of the invention〕

As explained above, the present invention is capable of dealing with input signal jitter that changes dynamically over time depending on line conditions or partner device conditions, by adding a loop filter stage number setting circuit to a conventional digital phase-locked circuit. Consecutive 3 rL
! ! Since the number of loop filter stages is automatically set to avoid the above phase lead or phase delay, it is possible to generate an extracted clock having an optimal amount of jitter and jitter frequency compared to the conventional method.

[Brief explanation of drawings]

Fig. M1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing an example of the filter stage number setting circuit shown in Fig. 1, and Fig. 3 is a block diagram showing an example of the filter stage number setting circuit shown in Fig. 2. A flowchart showing an example of the program operation of the control section, FIG. 4 is a block diagram showing an example of a conventional digital phase-locked circuit, and FIG. 5 shows a first stage of the loop filter of the conventional digital phase-locked circuit shown in FIG. FIG. 4 is a timing diagram showing the operation of main signals when the number of stages is one. 2... Change point detection circuit, 3... Phase comparator, 4... Loop filter, 5...
Oscillation circuit, 6. Old... Preset counter, 7...
... Filter stage number setting circuit, 71 ... Phase change instruction decoder, 72 ... Phase advance instruction signal counter, 73 ... Phase lag instruction signal counter, 74
...Continuous phase change instruction detection flip-flop,
75... Filter stage number setting control section.呵 2 old figure 3

Claims (1)

[Claims] a phase comparator that performs a phase comparison between an input signal and an extracted clock whose phase is synchronized with the input signal; a change point detection circuit that detects a change point at the rising edge of the input signal; Counts the number of phase lead signals or phase lag signals output from the phase comparator, and when the number is continuously counted beyond a predetermined number of loop filter stages, outputs a phase change instruction signal to increase or decrease the preset value from the nominal value. an oscillation circuit that outputs an original oscillation clock of the extracted clock; and a preset counter that uses the original oscillation clock as an input clock and uses the phase change instruction signal as a preset input signal to generate the extracted clock. In the phase locked circuit, the phase change instruction signal of the loop filter is continuously transmitted three times.
A digital phase synchronization circuit comprising a loop filter stage number setting circuit that automatically sets the number of loop filter stages so as not to instruct a phase advance or a phase lag of more than twice.