JPH05206849A - Circuit and method for free-running frequency stabilization for pll circuit - Google Patents

Abstract

PURPOSE:To reduce the deviation from a center value of the oscillation frequency of a voltage control oscillator which is caused by the influence of a circuit comprising a PLL circuit to the duty ratio of a feedback pulse, in the free-running state of the voltage control oscillator when the input of a transmission path extraction clock is disconnected. CONSTITUTION:The output of a voltage control oscillator 6 is inputted to an n1 frequency division circuit 10, and the input of the circuit 10 is inputted to an n2 frequency division circuit 9. While using one of the pulse frequency division ratio of the voltage control oscillator 6 as 'n1' and the other as 'n1Xn2', the 'n1Xn2' is inputted to an exclusive OR type phase comparator 3 when the input of a transmission extraction clock 1 is not disconnected; while the 'n1' is inputted to the same comparator when the input of a transmission extraction clock 1 is disconnected. The level conversion of the output of the comparator 3 is performed by a level conversion circuit 4, only a low band component is extracted in a low band filtration circuit 5 and such component is inputted to the voltage control oscillator 6 as control voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission device, and more particularly to a free-running frequency stabilizing circuit and method for a PLL circuit for extracting a synchronous clock from a received signal when receiving the digital signal. ..

[0002]

2. Description of the Related Art In a conventional PLL circuit, an output of an M divider circuit 2 for dividing an input transmission path extraction clock 1 by M and an output of a voltage controlled oscillator 6 are divided by N, as shown in FIG. N
An exclusive OR type phase comparator 3 which is performed by an exclusive OR gate for comparing the phase with the output of the frequency dividing circuit 11, and a level conversion circuit which performs level conversion of the output of this exclusive OR type phase comparator 3. 4, a low-pass filtering circuit 5 that passes only low-frequency components of the output signal of the level conversion circuit 4, and the voltage-controlled oscillator that changes the oscillation frequency according to the voltage level of the output of the low-pass filtering circuit 5. 6 and 6.

The present circuit compares the phase of the pulse obtained by dividing the transmission path extraction clock 1 by M and the pulse obtained by dividing the output pulse of the voltage controlled oscillator 6 by N to determine the oscillation frequency of the voltage controlled oscillator 6. It controls and operates so that the frequency of the output pulse of the voltage controlled oscillator 6 may be matched with the frequency of the transmission path extraction clock 1.

[0004]

In the conventional PLL circuit as described above, when the input transmission path extraction clock 1 is cut off, the exclusive OR phase comparator 3 and the N frequency divider circuit 11 are used. Is output to the level conversion circuit 4 as it is. Therefore, the exclusive OR type phase comparator 3 and the level conversion circuit 4 cause a difference in the delay amount between the rising edge and the falling edge of the pulse generated with respect to the input pulse. If the influence on the duty ratio of the input pulse to the device 3 is so large that it cannot be ignored, the oscillation frequency of the voltage controlled oscillator 6 in the free-running state when the input of the transmission path extraction clock is off has a large deviation from the desired oscillation frequency. There was a problem that it would occur.

An object of the present invention is to eliminate the above-mentioned conventional problems and to provide a duty ratio of a feedback pulse of a circuit constituting a PLL circuit in a free-running state of a voltage controlled oscillator when a transmission line extraction clock is disconnected. It is an object of the present invention to provide a free-running frequency stabilizing circuit and method for a PLL circuit in which the deviation of the oscillation frequency of the voltage controlled oscillator from the median value caused by the influence of the above is reduced.

[0006]

A first solving means of the present invention for solving the above-mentioned problems is to provide a first frequency dividing circuit for frequency-dividing a transmission path extraction clock and a first frequency dividing circuit. An exclusive-OR phase comparator that compares the phase of an output pulse with another divided pulse, a level conversion circuit that converts the level of the output signal of this exclusive-OR phase comparator, and this level conversion In a free-running frequency stabilizing circuit for a PLL circuit, which comprises a low-pass filter circuit that passes a low-frequency component of the output of the circuit, and a voltage-controlled oscillator that changes the oscillation frequency according to the voltage level of the output of the low-pass filter circuit. A second divider circuit for dividing the output pulse of the voltage controlled oscillator, a third divider circuit for further dividing the output pulse of the second divider circuit, and an input of the transmission path extraction clock With a clock loss detection circuit that determines the loss state The output of the second frequency divider circuit and the third frequency divider circuit is selected according to the input interruption state determination information of the clock interruption detection circuit and is input to the exclusive OR type phase comparator. It is characterized in that it is provided with a selector for making a round pulse.

A method for stabilizing a free-running frequency of a PLL circuit according to a second solution of the present invention for solving the above-mentioned problem is to provide the second frequency dividing circuit, the third frequency dividing circuit, and the selector. And the clock disconnection detection circuit is configured by an information processing device, the second divided pulse of the voltage controlled oscillator output is selected in the input disconnection state of the transmission path extraction clock, and when the transmission path extraction clock is input. The third frequency-divided pulse output from the voltage controlled oscillator is selected and input to the exclusive OR phase comparator.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the present invention.

The transmission path extraction clock 1 is input to the M frequency dividing circuit 2 and the clock break detection circuit 7, and the non-input break information from the clock break detection circuit 7 is input to the selector 8. The selector 8 receives the output signal of the n ₁ frequency dividing circuit 10 and the output signal of the n ₂ (= N / n ₁ , where N is the frequency dividing ratio of the conventional frequency dividing circuit) frequency dividing circuit 9 respectively. Cage,
And outputs to the circuit 9 and the circuit and the pulse that n ₁ × n ₂ divided by the 10, and a selection of the pulses n ₁ divided by n ₁ frequency divider circuit 10 exclusive-OR type phase comparator 3 .. The exclusive-OR phase comparator 3 compares the phases of the M-divided clock from the M-divider circuit 2 and the divided pulse from the selector 8 with an exclusive-OR gate, and outputs its output as a level. It is output to the conversion circuit 4. The level conversion circuit 4 level-converts the comparison result signal from the exclusive OR type phase comparator 3 so as to match the dynamic range of the control voltage of the transmission path extraction clock 1, and outputs it to the low-pass filtering circuit 5. The low-pass filter circuit 5 extracts only the low-frequency component from the level-converted signal and outputs it to the voltage controlled oscillator 6. The output of the voltage controlled oscillator 6 is again input to the n ₁ frequency dividing circuit 10.

The operation of the above arrangement will be briefly described below. When the transmission path extraction clock 1 is input, the clock break detection circuit 7 detects the input of the clock 1 and outputs non-input break information to the selector 8. The selector 8 outputs this by a non-input break information, the pulses n ₁ × n ₂ divided from the output signal of the n ₂ frequency divider 9 and n ₁ frequency divider circuit 10 to the exclusive OR type phase comparator 3. The exclusive OR type phase comparator 3 compares the phase of this n ₁ × n ₂ frequency-divided pulse with the M frequency-divided clock of the M frequency dividing circuit 2 and outputs it to the level conversion circuit 4. The signal whose level has been converted by the level conversion circuit 4 is further removed of high frequency components by the low pass filter circuit 5 and output as the oscillation control voltage of the voltage controlled oscillator 6. By such feedback, the oscillation frequency signal synchronized with the transmission path extraction clock 1 is output from the voltage controlled oscillator 6.

Further, when the transmission path extraction clock 1 is in the input interruption state, the clock interruption detection circuit 7 outputs the input interruption information to the selector 8.
Output to. Selector 8 from this input break information of the clock 1, pulses n ₁ divided output from the n ₁ frequency divider circuit 10 is directly input to the exclusive OR type phase comparator 3. Moreover, since there is no frequency-divided signal from the M-frequency divider circuit 2, the exclusive OR type phase comparator 3 outputs a pulse whose frequency is divided by n _{1 as} its output. Therefore, the control voltage of the voltage controlled oscillator 6 is fixed by this n ₁ frequency division pulse and becomes a free-running state.

[0012]

As described above, according to the present invention, when the transmission path extraction clock is input, the ratio of the frequency-divided signal of the output signal of the voltage controlled oscillator input to the exclusive OR type phase comparator to the ratio n. ₁ and × n _2, and in the input disconnection state of the transmission path extraction clock, n ₁ was the ratio between n ₁
The divided pulse from the frequency divider circuit is input to the exclusive OR type phase comparator to reduce the frequency division ratio of the input signal to the level conversion circuit which outputs the control voltage of the voltage controlled oscillator. As a result, the deviation of the oscillation frequency of the voltage controlled oscillator due to the delay difference between the rise and fall of the pulse generated in the exclusive OR type phase comparator and the level conversion circuit can be suppressed to 1 / n ₂ .

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional example.

[Explanation of symbols]

1 Transmission path extraction clock 2 M frequency divider circuit 3 Exclusive OR phase comparator 4 Level conversion circuit 5 Low-pass filter circuit 6 Voltage controlled oscillator 7 Clock break detection circuit 8 Selector 9 n ₂ Frequency divider circuit 10 n ₁ minute Circulation circuit 11 N division circuit

Claims (2)

[Claims] 1. A first frequency dividing circuit for dividing a transmission path extraction clock, and an exclusive OR phase for performing phase comparison between an output pulse of the first frequency dividing circuit and another frequency dividing pulse. A comparator, a level conversion circuit for converting the level of the output signal of the exclusive OR phase comparator, a low-pass filter circuit for passing the low-frequency component of the output of the level conversion circuit, and a low-pass filter for this low-pass filter. In a free-running frequency stabilizing circuit of a PLL circuit, which comprises a voltage-controlled oscillator that changes the oscillation frequency according to the voltage level of the output of the wave circuit, a second frequency-dividing circuit that divides the output pulse of the voltage-controlled oscillator, A third frequency divider circuit that further divides the output pulse of the second frequency divider circuit, a clock loss detection circuit that determines the input disconnection state of the transmission path extraction clock, and an input disconnection state determination of this clock disconnection detection circuit Second by information A PLL circuit comprising: a selector for selecting the outputs of the frequency dividing circuit and the third frequency dividing circuit and inputting to the exclusive OR type phase comparator as the other frequency dividing pulse. Free-running frequency stabilization circuit. 2. The second frequency dividing circuit, the third frequency dividing circuit, the selector, and the clock loss detection circuit are configured by an information processing device, and an input disconnection of the transmission path extraction clock is performed. In the state, the second divided pulse of the voltage controlled oscillator output is selected, and when the transmission path extraction clock is input, the third divided pulse of the voltage controlled oscillator output is selected and the exclusive OR type phase comparator is selected. A method for stabilizing a free-running frequency of a PLL circuit, characterized by inputting.