JPH0294709A - Phase locked loop device - Google Patents

Abstract

PURPOSE:To attain the phase control for plural number of times between the processings of phase comparison by executing the phase control according to the interval of phase control calculated from the result of phase comparison. CONSTITUTION:A phase comparison circuit 1 receives phase information inputted from a phase information input terminal 5 and a phase comparison timing being an output of a variable frequency division counter 4, discriminates multi- value quantization and outputs the result of phase comparison. The result of phase comparison is inputted to a phase control interval decision circuit 2 in which sequential processing is applied to output the direction of phase control and the time interval. A phase control interval counter 3 counts an output clock of the variable frequency division counter 4, resets the counter when the interval of the clock is coincident with a phase control time interval from the phase control interval decision circuit 2, outputs a control signal to the variable frequency division counter 4, outputs a clock synchronously with the frequency division ratio from an oscillator 7 and also gives an output to the phase comparison circuit 1 as a phase comparison signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronization device, and particularly to a phase synchronization device suitable for generating a clock that is phase-synchronized with data when receiving data.

[Prior art] Figure 3 shows, for example, the document How to use rPLL-IC (co-authored by Soza Hata and Keisuke Yoshikawa, published by Sanpo Publishing), page 14.
6-p, 151 is a block diagram of a digital type conventional phase synchronization device. In the figure, (5) is a phase information input terminal into which the phase information of the received data is input, (7) is an oscillator that generates a clock that is relatively faster than the input data, and (4) is the phase information input terminal from the oscillator (7). A variable frequency division counter that can divide the clock at an arbitrary frequency division ratio, (1) detects a phase difference by comparing the phase information from the phase information input terminal (5) with the output of the variable frequency division counter (4). Phase comparison circuit, (8) is a sequential loop filter that sets the frequency division ratio in the variable frequency division counter (4) based on the phase comparison result from the phase comparison circuit (1), (6) is a variable frequency division filter This is a clock output terminal that outputs a clock from the counter (4).

The operation of this configuration will now be described.

The phase information of the received data is input to the phase information input terminal (5), but normally the received data itself is input.

The phase comparison circuit (1) inputs this phase information and the phase comparison timing which is the output of the variable frequency division counter (4), and determines whether the received data is in the "advanced" phase or the "lag" phase. A binary quantized phase comparison result is output. The sequential loop filter (8) inputs the phase comparison result from the phase comparison circuit (1), outputs a phase control signal indicating whether or not phase control is necessary and the direction of phase control, and outputs a phase control signal that indicates the necessity of phase control and the direction of phase control. 4) Output.

The variable frequency divider counter (4) controls the oscillator (7) based on the phase control signal from the sequential loop filter (8).
) The phase control signal “advances” the frequency division ratio of the high-speed clock input from the phase control, and in the case of phase control, it decreases by “1,” and conversely, “
In the case of "delayed" phase control, it is increased by "1" and an output clock whose phase is synchronized with the phase information from the phase information input terminal (5) is sent out from the clock output terminal (6).

The sequential loop filter (8) is a bidirectional counter that takes a counting state from "10N" to "-N", and if the phase comparison result is "advanced", the count value is increased by one. If there is a delay, the count value is decreased by one, and the count value of this bidirectional counter is +
If the count value of this bidirectional counter becomes "-N", it generates an "advance" phase control signal and simultaneously resets the bidirectional counter to "θ".
Random walk filters (hereinafter referred to as RWF) that generate a delayed phase control signal and simultaneously reset a bidirectional counter to O'' are well known.

Now, Figure 4 shows a sequential 9-loop filter (8
), each positive and negative count value N is “2” RWF
3 is a timing chart showing temporal changes in the output phase of the phase synchronization device when using the phase synchronization device. Note that the phase in the figure is based on the initial phase on the receiving side and is standardized by the minimum phase control width, and the number of bits is the cumulative number of bits of input data. In addition, the dotted line shows the phase change that occurs due to the phase information input from the phase information input terminal (5) as data and the frequency offset when the variable frequency division counter (4) runs free, and the solid line shows the phase change that occurs due to the frequency offset when the variable frequency division counter (4) runs free. This is the phase of the output clock created by the frequency division counter (4). In addition, Fig. 4(a) shows the case where phase comparison can be performed constantly on the input data, and Fig. 4(b) shows the case where the phase comparison can be performed constantly for the input data.
This shows a case where phase comparison can be performed on only one bit, that is, a case where phase comparison can be performed only once every four bits of data.

[Problems to be Solved by the Invention] Since the conventional phase synchronization device is configured as described above, when a sequential loop filter such as RWF is used, the maximum But 1
There is a problem that phase synchronization cannot be performed when the phase comparison interval is long as shown in FIG. 4(b) or when the frequency offset is large.

The purpose of this invention was to solve the above-mentioned problems, and to provide a digital phase synchronization device that can perform phase synchronization even when the phase comparison interval is long or the frequency offset is large. The purpose is to obtain.

[Means for Solving the Problems] In order to solve the above problems, a phase synchronization device according to the present invention includes means for inputting phase information of input data;
A phase variable means changes the phase of the output clock of this synchronizer by changing the frequency division ratio, etc., and detects the lead and lag direction of the phase difference and the magnitude of the phase difference between the output clock and the phase information from the phase variable means. means for determining a time interval for phase control based on an output regarding the magnitude of the phase difference of the phase comparison means; It is provided with means for controlling the phase variable means in the direction of advancing and reducing the delay.

[Function] In the steam means, the phase synchronizer of the present invention advances the phase difference at time intervals based on the magnitude of the phase difference between the phase information of the input data and the output clock from this device, and adjusts the output clock in the direction of decreasing the delay. control the phase of

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a phase synchronization device according to an embodiment of the present invention. In the figure, (2) is the phase comparator circuit (1
), and (3) is a phase control interval counter that actually counts the time interval from the output of the phase control interval determining circuit (2). .

The operation of the above configuration will now be described.

The phase comparison circuit (1) manually inputs the phase information inputted from the phase information input terminal (5) and the phase comparison timing which is the output of the variable frequency division counter (4), and compares the phase information inputted with the phase comparison timing. Multi-level quantization is performed to determine how much the phase is leading or lagging, and outputs a phase comparison result that includes information about the direction of phase lead and lag and information about the size of the phase difference.This phase comparison The result is input to the phase control interval determination circuit (2) and subjected to sequential processing to output the phase control direction and phase control time interval.The phase control interval counter (3) calculates the phase control direction and phase control interval. is input, and the variable divider counter (
4), and when this count value matches the phase control time interval from the phase control interval determining circuit (2), the counter is reset and at the same time a phase control signal is output to the variable branch counter (4). . Variable frequency division counter (
4) is based on this phase control signal and sets the division ratio of the high-speed clock input from the oscillator (7) so that the phase control signal “leads by 1”.
In the case of phase control, it is decreased by "1", and in the case of "lag" phase control, it is increased by "1", and an output clock that is phase-synchronized with the phase information is output from the clock output terminal (6), and at the same time, this clock signal is A phase comparator circuit (1
).

In the time chart of FIG. 2, as the simplest example of the present invention, the phase comparison circuit (1) outputs a binary quantized phase comparison result of "advance" and "lag", (2) has "2" and "4" as the phase control interval, and when the phase comparison result changes from "delay 0" to "advance", the phase control interval is changed from "2" to "4", and vice versa. The following example shows a case in which a device that changes from "4" to "2" is used.Here, the phase comparison can be performed on the "5" bit and the "1 degree bit", and (a) to (g
) is shown in the figure as a phase comparison point. On the other hand, the phase control interval is also shown.

First, when the phase control interval is set to "2" as the initial value,
In the comparison of (a), the phase comparison result changes from "lag" to "advance", so the phase control interval is set to "4". Next, in the comparison (b), the phase comparison result “advances”
Since it became "delayed", this interval was set to "21" and (C
) In the comparison, the phase comparison result changed from "lag" to "advance", so the phase control interval is set to "4". On the other hand, (d)
In the comparison (e), the phase comparison result does not change, so the phase control interval is not changed, and in the comparison (f), the phase comparison result changes from "advance" to "lag 1", so the phase control interval is set to "2#". do. However, since the content of the phase control interval counter (3) is "3" at the time of comparison in (b), the phase control interval is 3.

By performing the above operations, the phase of the output clock obtained from the clock output terminal (6) synchronizes and follows the phase information input from the phase information input terminal (5).

[Effects of the Invention] As described above, according to the present invention, phase control is executed according to the phase control interval calculated from the phase comparison result, so phase control is performed multiple times between phase comparisons. This is effective for digital phase synchronization when the phase comparison interval is large or when the frequency offset is large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a phase synchronization device according to an embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of the configuration of FIG. 1, and FIG. 3 is a block diagram of a conventional phase synchronization device. FIG. 4 is a timing chart illustrating the operation of the configuration shown in FIG. In the figure, (1) is a phase comparison circuit, (2) is a phase control interval determination circuit, (3) is a phase control interval counter, and (4) is a phase control interval determination circuit.
is a variable frequency division counter, (5) is a phase information input terminal, and (6
) is a clock output terminal, (7) is an oscillator, and (8) is a sequential loop filter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Patent attorney Masuo Oiwa (and 2 others) 1. Phase comparison circuit 2 Phase control interval determination circuit 3 Phase control interval counter/talo: clock output terminal 7 Block diagram of an embodiment of the m generator Kono invention Phase comparison Circuit Variable Frequency Divider Circuit Phase Information Input Terminal Output Terminal Oscillator Nuken/Yaruru Loop Filter Block Diagram of Conventional Device Fig. 3 Phase 1. Indication of the case Patent application No. 26 Name of the invention Phase synchronizer 3, person making the amendment Phase representative Moriya Shiki 4, agent Figure 3 Operation timing chart of the structure Figure 5: Specification subject to amendment Column for detailed description of the invention. 6. Details of amendments and above

Claims (1)

[Claims] means for inputting phase information of input data; phase variable means for changing the phase of an output clock; phase comparison means for detecting the direction and magnitude of the phase difference between the output clock and the phase information from the phase variable means; Interval determining means for determining a time interval for phase control based on the output of the comparing means; and means for controlling the phase variable means in a direction to reduce the phase difference detected by the phase comparing means at the time interval based on the output of the interval determining means. A phase synchronization device comprising: