JPS6037665B2 - Phase synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase synchronization method in signal processing for data transmission, and for example, to a phase synchronization method in a data modem or the like that transmits data using a telephone line.

Generally, a data modem captures data in its transmitter in synchronization with a transmission element synchronization signal from a data terminal device, modulates the captured data, and transmits the modulated data.

Further, the receiving section of the data modem extracts the modulation rate component from the received signal and demodulates the received signal in synchronization with the extracted modulation rate component. According to the recommendations of CCITTV27 and V29, the synchronization accuracy in the transmitter and receiver is defined as ±0.01%.

To achieve this synchronization accuracy, conventional low-pass filters,
Analog devices such as voltage controlled oscillators (VCOs) have been used, but analog devices have the disadvantage of being susceptible to external disturbances.
An object of the present invention is to digitally synchronize the phase of a reference signal such as a transmission element synchronization signal or an extracted modulation rate component as described above with the phase of processing such as data acquisition and demodulation, thereby improving data transmission. The aim is to achieve stable and high synchronization accuracy in signal processing.

In order to achieve the above object, in the present invention, a reference signal is read in a calculation circuit whose instruction repetition execution processing frequency is known, and the phase of the read reference signal and the phase of the repetition execution processing of the calculation circuit are calculated. As a result of the comparison, if the phase of the repetitive execution process is earlier than the phase of the reference signal, a specific instruction is executed to decrease the frequency of the repetitive execution process, and the phase of the repetitive execution process is A phase synchronization method is proposed in which the execution of a specific command is omitted when the phase is slower than that of the reference signal, and the repeat execution processing frequency is increased.

Hereinafter, one embodiment of the phase synchronization method according to the present invention will be described in comparison with a conventional method based on the accompanying drawings.

FIG. 1 is a block diagram showing a conventional phase synchronization circuit, which has a well-known PLL circuit configuration.

In FIG. 1, the phase of the reference signal of frequency fR and the phase of the follow-up signal of frequency fv are compared by phase comparator 1, and the high frequency components contained in the phase difference signal obtained from this comparison result are low frequency components. It is removed by filter 2, and the output voltage of low-pass filter 2 controls VC03. The output frequency of the VC03 is divided by 1/N' by the counter 4 and becomes the frequency fv of the follow-up signal, which is fed back to the phase comparator 1. In this way, the follow-up signal is analog-synchronized with the reference signal, but as mentioned above, the low-pass filter 2 and VC03 are easily affected by external noise, so the synchronization operation is unstable, so it is difficult to adjust VC03. The operation is complicated, and high synchronization accuracy cannot be obtained. FIG. 2 is a block diagram showing a digital phase synchronization circuit for schematically explaining the phase synchronization method according to the present invention.

In FIG. 2, the output frequency of the oscillator (OSC) 11 is slightly higher than N times the frequency fR of the reference signal. Oscillator 1
The output signal from 1 is input to a counter 13 via a tooth extraction circuit (RMT) 12. The counter 13 divides the input signal frequency into 1/N and outputs the divided signal. The frequency fv of the output signal of the counter is compared with the frequency fR of the reference signal by a phase comparator 11, and the phase difference signal resulting from this comparison is fed back to the control input of the tooth extraction circuit 12 as a control signal. When the frequency fv is higher than the frequency fR, the number of pulses corresponding to the frequency difference is removed from the output signal of the oscillator 11 by the tooth extraction circuit, so the frequency fv becomes lower. By repeating this loop, phase synchronization can be achieved between the output signal of the counter and the reference signal. FIG. 3 is a more detailed block diagram for explaining one embodiment of the phase synchronization method according to the present invention.

2 and 3, the counter 13 in FIG.
Delay circuit D. , D2, D3, . . . , Dn. Delay circuit D. Or Dn
Each delay circuit tD is substantially constant. The tooth extraction circuit 12 in FIG. 2 corresponds to the tooth extraction circuit 12 shown in FIG. 3, which includes the switch 21, the delay circuit Do, and the OR gate 22. The phase comparator 14 in FIG. 2 corresponds to the reading circuit 23 and switch changeover circuit 24 in FIG. 3. In FIG. 3, reading circuit 23 receives an external reference clock signal of frequency fR and compares it with a signal of frequency fv from delay circuit Dn. As a result of this comparison, the switch changeover circuit 24 connected to the reading circuit drives the switch 21 so that fR
is larger than fv, the output of the delay circuit Dn is switched to switch 2.
If fR is smaller than fv, the output of the delay circuit Dn is connected to the contact 27 of the switch 21. In the former case, the frequency fv of the repetitive execution process is determined by the delay circuits D, , D2 . ..., one round total delay time nt of Dn.
In the latter case, the frequency fv is the total delay time (n
11)t. is equal to the reciprocal of Therefore, a variable frequency signal having an upper limit of frequency 1/n and a lower limit of frequency 1/(n+1)to is obtained as the output of the delay circuit Dn. That is, the circuit of FIG. 3 operates as a variable frequency oscillator (VFO). When the delay time to and the clock cycle are the same, as in the case of constructing a delay circuit using a shift register, the output cycle of the clock oscillator (OSC) 28 that drives each delay circuit is such that the frequency fR of the reference signal is 1/nt. and 1/(n
+1) Determine the delay time tD so that it is approximately the intermediate value of to. By the above operation of the circuit shown in FIG. 3, the rise of the output signal of the delay circuit Dn is synchronized with the rise of the reference signal.

That is, if the rise of the output signal of the delay circuit Dn of FIG. 4B is ahead of the rise of the reference signal of FIG.
The frequency of v is decreased and the delay time t of the delay circuit Do
The phase of the output signal of the delay circuit Dn is delayed by o. Also,
Conversely, when the rise of the output signal of the delay circuit Dn is delayed by the time t2 with respect to the rise of the reference signal, the delay circuit D
The phase of the output signal of n is advanced. Synchronization is achieved by advancing or delaying the phase of the output signal of the delay circuit Dn in this manner. If phase synchronization is to be achieved between the rising edge of the reference signal and the rising edge of the output of the delay circuit, the connection of the switch 21 to the contacts 26 and 27 may be reversed to that described above. The circuit of FIG. 3 can actually be realized by a microcomputer such as the MB8881 manufactured by Fujitsu Limited or the Intel i8048 series.

In this case, each of the delay circuits D, D2, . The delay circuit Dn-, is replaced by a reference signal read instruction, and the delay circuit Dn is replaced by a conditional branch instruction for phase comparison. FIG. 5 shows an example of a flowchart of the operation when realizing a phase-locked circuit in a microcomputer. In FIG. 5, in the first step, a phase comparison is made between the frequency fR of the reference signal input from the outside of the microcomputer and the frequency fv of the repetitive execution process of the microcomputer, and as a result of this comparison, if fv is advanced, then Go to the second step, and if you are behind, jump to the third step. Any processing can be performed from the third step to the n-th step, but the total execution time is made equal to the sum of D to Dn-2. At the (n+1)th step, a reference signal is also negotiated. After the (n+1)th step, the process returns to the first step again. According to the comparison result in the first step, the frequency of the repetitive execution process is increased or decreased by performing or not performing the Do process in the second step, thereby achieving phase synchronization. The discussion of the reference signal is the nth eleventh.
It may be performed in steps other than step. In addition, in FIGS. 3 and 5, as a result of the comparison between the reference signal frequency and the repetitive execution processing frequency, only "Do" is considered as the process that may be omitted, but other invalid commands are also provided to increase the synchronization accuracy. It is also possible.

As is clear from the above description, according to the present invention, it is possible to synchronize the phase of the reference signal and the phase of repetitive data processing using a digital device, thereby achieving stable and high synchronization in signal processing for data transmission. Accuracy is achieved.

Further, by establishing phase synchronization using software by a microcomputer, other functions such as modulation and scrambler functions can be included in the same microcomputer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional phase locking circuit, FIG. 2 is a block diagram showing a digital phase locking circuit for schematically explaining the phase locking method according to the present invention, and FIG. 3 is a block diagram showing a phase locking circuit according to the present invention. A more detailed block diagram for explaining one embodiment of the synchronization method, FIG. 4a is a waveform diagram showing an example of a reference signal, and FIG. 4b is a waveform diagram showing an example of the output signal of the delay circuit Dn. , FIG. 5 is a flowchart of one embodiment of the operation when the circuit of FIG. 3 is implemented by a microcomputer. 1: Phase comparator, 2: Low-pass filter, 3: Voltage controlled oscillator, 4: Counter, 11: Oscillator, 12: Tooth extraction circuit, 1
3: Count, 14: Phase comparator, 21: Switch, 2
3: Discussion circuit, 24: Switch switching circuit, 26, 27:
Contact of switch 21, 28: Clock oscillator, Do, D
,,...,Dn: delay circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1 A reference signal is read in a calculation circuit whose repetitive execution processing frequency of the instruction is known, the phase of the read reference signal is compared with the phase of the repetitive execution processing of the calculation circuit, and as a result of the comparison, the repetition execution processing frequency of the instruction is known. If the phase of the process is faster than the phase of the reference signal, execute a specific instruction to reduce the repetitive execution processing frequency, and if the phase of the repetitive execution process is slower than the phase of the reference signal, execute the specific instruction. A phase synchronization method characterized in that the repeat execution processing frequency is increased by omitting the above.