JPS61129936A - Data recovery circuit - Google Patents

Abstract

PURPOSE:To obtain automatically an optimum phase of a sampling clock by supervising a sampling value of transmitted data. CONSTITUTION:A difference between an input signal of a multi-value data setting circuit 24 and an expected value of an input signal is obtained by a difference device 26, whose output is inputted to plural accumulators 27, 28 accumulating the signal at a different phase position. The least accumulated data in the accumulators 27, 28. is used as error data t the position close to the optimum sampling phase and phase shift information of the sampling clock depending on the relation between an eye pattern and the sampling phase. Thus, even if variance in the reception characteristic and a phase error residual of a PLL circuit exist, data recovery with less error rate and no adjustment is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data reproducing circuit used for reproducing digital data superimposed on, for example, a television signal.

[Technical background of the invention and its problems]

In satellite broadcasting systems, when transmitting television signals, a method has been proposed in which synchronization signals and audio signals are superimposed and transmitted as digitized data 1o within the retrace interval (T), as shown in Figure 3. has been done. (AV8) is
It is a analog television signal, and (DV8) is a digitized television signal. When reproducing such digital data, first, a clock component is extracted from the data portion of the spear 1 and clock reproduction is performed. A PLL (phase-locked droop) circuit is usually used for clock recovery, and the clock component in the data and the PLL
Phase comparison of the oscillation outputs of the LL circuits is performed to ensure that the data and clock phases are equal. Using the clock generated in this manner, as shown in Figure 4, digital data is reproduced by sampling with a data sampling clock at the phase position where the eye opening ratio of the data is greatest.

By the way, the clock reproduced by the PLL circuit does not always have the optimum phase as shown in Figure 4.

For example, if the sparse pattern is distorted due to echoes or receiver phase distortion, or if phase errors in the PLL circuit remain, a clock with the optimal phase cannot be obtained and the data error rate increases. Resulting in. In particular, in the case of multi-level transmission such as the one shown in 5-, the horizontal spread of the eye pattern is small, so the clock phase shift becomes a big problem.

Figure 6 shows a conventional example of a clock recovery circuit for demodulating digital data. The input signal is waveform shaping filter 1
2t-way, the clock component is input to the latch circuit 13 and the clock component extraction circuit 14. The clock component extracted by the clock component extraction circuit 14 is input to the PLL circuit 15. The PLL 1gl path 15 inputs the data clock. However, as shown in Figure 4, the phase of this clock does not necessarily have an optimal phase relationship with the data signal. Therefore, the phase of this clock is -gk by the phase shift circuit 16, and the clock is set so that the rising edge of the clock is located at the widest point of the eye pattern.

Adjustment of the phase shift circuit 16 is performed manually during the manufacture of the receiver, but this process is a major factor in increasing costs during mass production.

Another problem is that it cannot adapt to phase shifts caused by molding distortion caused by changes in reception conditions and phase shifts caused by changes in circuitry over time. Therefore, there is a need for a clock phase side control system that monitors the phase of the clock and always keeps it at the optimum phase.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a data reproducing circuit that can automatically maintain the phase of a reproduced clock for data reproduction at an optimum phase at all times.

[Summary of the invention]

In order to achieve all of the above-mentioned objects, the present invention uses a subtracter to calculate the difference between the value of the input signal of the multi-value data judgment circuit 240 and the expected value of this input signal, as shown in Figure 1. 26, and the output of this difference device 26 is input to a plurality of accumulators 27 and 28 which accumulate at different phase positions.

Based on the relationship between eye butter/ and the sampling phase, it is assumed that the smallest accumulated data in the accumulators 27 and 28 is error data at a position close to the optimum sampling phase, and this is used as phase shift information for the sampling lock. It is.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, a composite video signal is input to an input terminal 21, and this signal is converted into an analog-to-digital converter 22. Here, the sampling clock (CKO) used in the analog-to-digital converter 22 is a transmission lock 8 of data superimposed on the video signal.
For example, a frequency twice the wave number is used.

The digitized video signal is guided to a digital video processing section (not shown), and a digital filter 2
3 is input. This digital filter 23 is only for extracting all of the sampled data, and shapes the waveform of the transmitted data.

In this case, in order to create a digital filter, a clock with a frequency at least twice that of the transmission lock is required, but the data input here must be set in advance at two times the frequency of the transmission lock.
Since the sampling clock (CKO) with twice the frequency is used, it can be realized with a normal shaping filter (for example, cosine roll-off) characteristics. The output of the digital filter 23 is input to a multi-value data determination circuit 241C, where the level is determined and an estimated value of the transmission data is obtained. Next, the output data of the multi-valued data determination circuit 24 and the output data of the digital filter 23 are inputted to a differentiator 26/C to obtain difference data. The output of the differentiator 26 is then input to an accumulator 27 and an accumulator 28. In this case, the phases when the accumulators 27 and 28 take in the difference data are the timing when the clock (CKA) rises, and
This is the time when the clock (CKB) rises. The clocks (CKA) and (CKB) are obtained by dividing the previous sampling clock (CKO) into 1/2 by the flip-flop circuit 3111C, and their waveforms are as follows.
They are in an anti-phase relationship with each other. (Refer to Figure 2) The data accumulated in the accumulators 27 and 211 are judged by the comparator 29 as to whether the value is large or small.Comparator 2
9 determines the magnitude of the absolute values of the cumulative data (A) and (B), and switches the selector 30 so that the cumulative data with the smaller value is selected by the selector 30. Therefore, the accumulated data with the smaller value is input to the digital-to-analog converter 31 through the selector 30. The output signal of this digital-to-analog converter 31 is input to the phase control terminal of the phase shift circuit 32, and the signal is input to the phase control terminal of the phase shift circuit 32.
control the phase of CKO).

Further, the judgment output of the comparator 29 is also given to a control terminal of a latch pulse selection switch 39. This latch pulse selection switch 39 is connected to the clock (C
Either one of KA) and (CKB) is selected and supplied to the latch circuit 25 as a latch pulse.

For example, when the selector 30 selects the accumulated data of the accumulator 27, the latch pulse selection switch 39 selects the clock (CKA) t-% used for the accumulator 27, and the selector 30 selects the clock (CKA) t-% to be used for the accumulator 27. If 28 cumulative data is selected, press latch pulse selection switch 3.
9 selects the clock (CKB) used for accumulator 28. The latch circuit 25 is connected to the multi-value data determination circuit 24.
Latch the output data from.

The sampling clock (CKO) is generated by a clock generation circuit using a phase locked loop. That is, from among the video signals input to the input terminal 21,
A clock component serving as the data reference phase is extracted by a clock component extraction circuit 33, and the extracted clock component is supplied to one input terminal of a phase comparator 34.

The voltage controlled oscillator 36 outputs an oscillation signal with twice the frequency of the transmission lock, and this oscillation signal is used as a sampling clock (CKO) through the phase shift circuit 32t, and is also used as a sampling clock (CKO) through the 172 frequency divider. 37t-, the frequency is divided by l/2, and the signal is supplied to the other input terminal of the phase comparator 34 described above. The phase comparator 34 listens to the phase difference signal between the two human power signals, and this phase difference signal is smoothed by a low-pass filter 35 to become a direct pressure, which is the voltage-controlled oscillator's 360-cycle frequency phase. Input to control terminal.

As described above, the data reproducing circuit of the present invention not only obtains a seven-stem phase synchronization state using the clock component, but also monitors the sampling data to make the data sampling phase accurate. The difference between the value and a predetermined value is accumulated, and the phase control information t- of the sampling clock is obtained from the accumulated result.

The operating principle and effect will be explained below with reference to Figure 2.

Now, consider a case where the transmitted data is 4-value data.

The analog waveform of the input signal forms an eye pattern as shown in Figure 2(a). , 1'F2 Figure (b) is the sampling clock, and Figure (d) is the sampling clock.

(eJ is the previous black y (C'KA), (C
KB).

Assume now that the rising phase of the sampling clock (CKO) is shifted from the largest aperture position of the eye pattern, as shown in the figure.
The following explanation assumes that the rising phase positions of clocks (CKA) and (CKB) are at the positions shown in the figure with respect to KO). Not applicable. For example, the time point (
Even if data at the level of Dl is sent at the receiving station, the sandal value of the waveform at the receiving station is 8 A as shown in the figure.
It becomes the level of l. If the clock position is optimal,
1) l=41, and the difference should be zero. The differentiator 26 is a circuit that detects this difference.

Therefore, the sample value and the level to be expected (e.g. 1
) The optimum sampling phase can be set by detecting the difference in (1) and adjusting the phase of the sampling clock (CKO) so that this difference becomes zero. In this case, the sample point at the center of the eye pattern will be the ice sheet data, but the sample points between the eyes will be indefinite and have no meaning, so as shown in Figure 2 (C), one sample point will be used. Data from every other sampling point is adopted.

Now, suppose that, for example, a sampling value (Al) is obtained at the tenbling time point (to). For this data, the multi-value data determination circuit 24 determines the sum/bring value (artificial).
The expected value, for example, Dlfc, closest to is determined, and the judgment data value (Dl) of this level is outputted as L-. Here, differentiator 2
6 performs the calculation of Dl-person 1 and obtains the error signal (Dl-
Al) t-Takata. The absolute value of this error signal is input into the accumulator 27 in this case. When such processing is performed one after another, the accumulated data (A) in the accumulator 22 and
A difference arises between the accumulated data (B) in the accumulator 28 and the accumulated data (B).

In other words, under the phase relationship shown in Figure 2, the clock (CK
The sample value based on the phase of A) is close to the correct value, and the sample value based on the phase of the clock (CKB) has almost no meaning since the eye is not open. As a result, the *& value of the error signal at the sampling point by the clock (CKB), that is, the output of the accumulator 28, is much larger than the output of the accumulator 27, which accumulates the error signal at the approximately correct sampling point. Become. Therefore, the comparator 29 switches the selector 30f so that the smaller value, that is, the output of the accumulator 27, is input to the digital-analog converter 3, and the switch 39 switches the clock (
CKA) t-Set to select. Therefore, a latch pulse is applied to the latch circuit 25 at a phase position where data exists. In addition, the digital-to-analog converter: It outputs a phase control signal corresponding to the error signal, and based on this signal, the phase of the sampling clock (CKO) is set to the most open position of the eye. The error signal (Dl-personl) is shifted to zero.

The present invention is not limited to the above embodiments, and the frequency of the sampling clock (CKO) is not limited to twice the transmission data clock frequency, but is n times the transmission data clock frequency (n is any positive *
H) may be used.

In this case, n clocks having a period n times that of the S/GRING clock 00 and different phases are created, and n accumulators corresponding to each clock are prepared. And Tanigumi! The smallest output of the X-device may be selected and used as the phase control information of the sampling clock. Of course, in this case, the switch for taking out the latch pulse is also
It has n clock input parts, and any one can be selected as tS. In this way, even finer phase adjustment can be performed over the counter.

〔Effect of the invention〕

As described above, according to this system, the optimal phase of the sampling clock can be automatically obtained by monitoring the seven-noring value of the transmitted data. Therefore, even if there are variations in reception characteristics and residual phase errors in the PLL circuit, data reproduction can be achieved without stabs and with a low error rate. In addition, since this circuit uses a sampling clock that is n times as large as the transmission data clock in advance, there is no need to use a new n-times clock generation means used in the digital filter, which is effective in simplifying the configuration. be. Furthermore, since the pulse shaping filter, multi-value determination circuit, etc., which were conventionally composed of analog parts, are digitized, the number of parts can be reduced by 81j by LSI, which is effective in significantly improving reliability.

[Brief explanation of the drawing]

Figure 1 is a configuration explanatory diagram showing one embodiment of the present invention, Figure 2 is a timing diagram shown to explain the operation of the circuit in Figure 21, Figure 3 is an explanatory diagram of a video signal, Spear 4 Figure 1.
? 5 is an explanatory diagram of the synchronization relationship between the eye pattern and the sampling clock, and FIG. 6 is an explanatory diagram of a conventional data reproducing circuit. 22...Analog-digital converter, 23...Digital filter, 24...Multi-value data judgment circuit, 2'5.
... 2-way circuit, 26... Differential device, 27.28...
Cumulative R1z9...Comparator, 30...Selector, 31...Digital-to-analog converter, 32...Phase shift circuit. Applicant's Representative Patent Attorney Takehiko Suzue Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] Oscillation means for generating a basic clock with a frequency n times (n is a positive integer) a data clock of transmission data; and a clock input from the oscillation means that can be phase-shifted; a phase shift circuit that derives the input signal as a sampling clock; an analog-to-digital conversion means for sampling an input signal using the sampling clock to obtain an analog-to-digital conversion output; and determining the level of the digital input signal output from the analog-to-digital conversion means. data determining means for outputting a signal with an expected value that the signal should originally have; a difference device calculating a level difference between the input signal of the data determining means and the expected value signal; means for generating n clocks each having a different period and phase; n accumulators each corresponding to each of the n clocks and accumulating the output of the differentiator according to each clock; means for determining cumulative data having the smallest absolute value among the cumulative data of n accumulators and inputting the cumulative data to a digital-to-analog converter; and means for phase-shifting the output of the digital-to-analog converter to the phase shift circuit. 1. A data reproducing circuit comprising: means for inputting an amount control signal.