JPS60142623A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To constitute a simple, small-scale PLL circuit by performing phase comparison, frequency division, and phase operation by a simple circulating shift register circuit composed of flip-flops and gate circuits. CONSTITUTION:An oscillator 6 outputs a clock S6 of frequency which is six times as high as the basic frequency of an input clock phiIN. The circulating shift register circuit 10 operates by receiving the clock S6 and the output S7 of a change point detecting circuit 7 to generate an output clock phiOUT. While the output S7 of the change point detecting circuit 7 is 0, six flip-flops F1-F6 operate while connected in a main loop and are held in current phases. When a change point is detected, the output S7 is 1. At this time, when the flip-flop F1 as the 1st stage is set, the main loop is maintained and at this time, the input clock phiIN and output phiOUT synchronize with each other. Otherwise, they do not synchronize with each other, and the loop is changed to perform follow-up operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention particularly relates to a digital PLL (phase, locked, loop) circuit consisting solely of digital circuits.

2. Description of the Related Art Structure and its Problems Conventionally, the structure shown in FIG. 1 has been known as a digital PLL circuit. This PLL circuit has an input clock φI
Frequency basic tarot S1 which is an integer multiple of the basic frequency fa of N
a fixed oscillator 1 that generates a fixed oscillator 1, a phase comparator 2 that outputs a phase difference signal S2 with a duty ratio corresponding to a phase difference between an input clock φIll and an output clock φOUT generated as described below, and A counter unit 3 that determines whether the phase is advanced or delayed; a clock converter 4 that performs signal conversion that involves manipulating the number of pulses of the basic clock S1 according to the output signal of the counter unit 3; and a clock converter 4 that performs processing. The frequency divider 5 divides the converted clock S6 to obtain an output clock φ011T.

The phase comparator 2 uses an EOR (exclusive OR) circuit as a simple configuration, and outputs an EOR signal of the input clock φI)l and the output clock φOUT as a phase difference signal S2. The relationship between these signals φrN+φ0UTIS2 is shown in FIG. Figure A to C are output clocks φ0t
A state in which the phase of lT is ahead of the phase of the input clock φIN is shown, a synchronous state is shown in 2~, and a state in which the phase of φOUT is φ! This shows a state where it is behind H.

As is clear from FIG. 2, from the time difference between the H level section and the L level section in the phase difference signal S2 for one period, φIN
It is possible to know the phase difference between and φOUT.

The counter section 3 detects this.

The counter section 3 is composed of a binary up/down counter circuit, and performs an up-count operation with a predetermined clock when the phase difference signal S2 is at the H level, and performs a down-count operation when the phase difference signal S2 is at the L level. Then, when counting up to K in the up direction, a carry signal S3 is output, and when counting down to Kt, a borrow signal S4 is output. 11-1 to the count value: Input clock φ! N
The period is set to correspond to more than half a period of time.

Therefore, if the phase of the output clock φOUT leads the phase of the input clock φIN by a certain value or more, the borrow signal S
4 turns on, and on the other hand, when there is a delay, the carry signal S3
is turned on.

Carry signal 83. When both borrow signals S4 are off (when the phase of φout is synchronized with φIH), the clock converter 4 performs a process of deleting one pulse for every two pulses of the basic clock S1 to obtain the converted clock S6. .

In other words, in this state, the converted clock S6 is a signal obtained by subdividing the basic clock S1, and the signal obtained by dividing this into λ by the frequency divider 6 becomes the output clock φOUT. As is clear here, the fixed oscillator 1 oscillates at 2XN times the fundamental frequency fa of the input clock φIII.

When the carry signal S3 turns on (the phase of φOUT becomes φ
If it is later than IN), the clock converter 4 is
.

The basic clock S1 is directly used as the switching clock S6 without performing pulse deletion processing. In other words, the basic clock S
Compared to the synchronized state in which one pulse is deleted every two pulses of S1, the conversion clock S5 is changed every two pulses of the basic clock S1.
1 pulse will be added to . This is the output clock φ. The phase of U7 is advanced to follow φ□.

When the borrow signal S4 turns on (φoI, the phase of T changes to φ
(proceeding further), the clock converter 4 converts the basic clock S
Delete two pulses of 1 in succession. That is, compared to the synchronous state described above, one pulse of the conversion clock S6 is deleted for every two pulses of the basic clock S1. This delays the phase of the output clock φOUT and makes it follow φIN.

The reason why the converted clock S6 is divided by four by the frequency divider 5 and finally becomes the output clock φOUT is that the PLL is operated with a clock that is 2XN times the fundamental frequency fa of the input clock φxx. This is to reduce the jitter of the output clock φOUT, and it is generally desirable to increase the value of H as much as the circuit system allows.

The conventional digital PLL circuit described above has a phase comparator 2.
1 Counter section 3. It is composed of a combination of many circuits, each having a different function, such as a clock converter 41 and a frequency divider 5, which has the problem of increasing the circuit scale. The large scale of the circuit is a fundamental drawback, as it causes various problems such as an increase in chip size even when the entire circuit is integrated into an LSI.

Further, there is a problem that conventional circuits cannot cope with the increase in input clock speed. One of the reasons for this is that a basic clock with a high frequency of 2XN times the basic frequency of the input clock is required. Furthermore, many circuits having a counter configuration with deep logic, such as the counter section 3 and the frequency divider 5, are included, and this point is also a cause of impediments to speeding up.

OBJECT OF THE INVENTION An object of the present invention is to provide a digital PLL which has a simple circuit configuration and can easily cope with higher speed input clocks.
The purpose is to provide circuits.

7.\-7 Structure of the Invention The present invention includes a change point detection circuit that detects a change point of an input clock, a fixed oscillator that generates a basic clock having a frequency that is an integral multiple of the basic frequency of the input clock, and a plurality of flip-flops. A PLL is constituted by a cyclic shift register circuit which includes a 70 tube and a plurality of gate circuits, and in which specific signal bits are cyclically shifted in synchronization with the basic clock. Here, the gate circuit is arranged to receive the output of the change point detection circuit and control the shift destination of information between each of the seven resource blocks, and the gate circuit is arranged to control the shift destination of information between each of the seven resource blocks, and the position of the specific signal bit in the cyclic shift register circuit. and a loop that delays the shift of the specific signal bit in a predetermined 7-resprop block, and a loop that delays the shift of the specific signal bit by using a predetermined 7-lip 70 block, depending on the relationship between the output timing and the output timing of the change point detection circuit. Form a forward loop.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows the configuration of a digital PLL circuit according to an embodiment of the present invention, and FIG.
42G23(3) waveform is shown. In order to simplify the explanation, this embodiment is configured to operate at a speed six times the fundamental frequency of the input clock φIH.

In FIG. 3, the fixed oscillator 6 outputs a basic clock S6 having a frequency six times the basic frequency of the input clock φIN, which is a data string. This PLL circuit operates in synchronization with the basic clock S6.

The input clock φI)l is applied to the change point detection circuit 7. As shown in FIG. 4, in response to both the rising and falling changing points of the input clock φx)I, the changing point detection circuit 7
An edge signal S7 is output from.

This edge signal S7 is a pulse signal with a width equal to the period of the basic clock S6.

10 circular shift register circuits, six D-shaped flip-flops F1 to F6, and OR gates G1, G4. G11 and AND gate G2. G5. G7°G9 and NOR gate G3. G6. G8. G10, operates in response to the basic clock S6 and the output S7 of the change point detection circuit 7,
Create an output clock φOUT. Only one of the six flip-flops F1 to F6 is set, and its "1" bit is cyclically shifted in the loop in synchronization with the basic clock S6. However, the above loop is not constant, but changes as follows, and phase tracking processing is performed.

The main loop of the circular shift register circuit 1o is a state in which six flips 70 tubes F1 to F6 are all connected in a ring, and normally operates in this state.

In that case, the basic clock S6 is used for discrimination in this circuit 1o, and the frequency-divided signal is taken out from the fourth stage flip 70 tube F4 as the output clock φ0 (IT).

The output Sy (edge signal 87) of the change point detection circuit 7 is 1"
During the period when the value remains at 0'', the cyclic shift register circuit 10
operates in the main loop described above and maintains the current phase. Also, when edge S7 becomes "1", the first stage flip-flop.

When Fl is centered (point A in FIG. 4), the main loop of the circular shift register circuit 1o is maintained and there is no change in phase. While maintaining this state, cycle 10.

When the ring shift is performed, the phase of this circuit 10 is synchronized with the input clock φIN.

Different from the above state, when the edge signal S7 becomes 11111, the 2nd to 6th stage Frisoflof.

When any one of F2 to F6 is sent, the phase of this circuit 100 is not synchronized with the input clock φIN.

The reason why the 7-lip flop F2 is set when S7-“1” is the input clock φ! The phase of H is this circuit 10
(point B in Fig. 4). In this case, the gate G3 is turned off when S7="1'", and the set state of the flip-flop F2 is not transmitted to the next stage flip-flop F3. Instead, the gate G2 is turned on, and the output Q of the flip-flop F2 is A "1" is returned via gate 02°G1 to the input of flip-flop F2 itself. That is, the main loop of the circuit 1o is temporarily cut off, and a self-delay loop connecting the input and output of the clip prop F2 is formed. As a result, the shift operation of the circuit 10 is delayed by 117.7 cycles of the basic clock S6, and the phase of the circuit 1o (i.e., the output clock φ
OUT) follows the input clock φIN.

The reason why the 7-lip flop F3 is set when S7 is "1" is that the phase of the input clock φIH lags behind the phase of the circuit 10, as described above. In this case, gate G4. G6. (Re causes the main loop connecting the flip-flops F3 and F4 to be temporarily cut off, forming a self-delay loop connecting the input and output of the flip-flop F3 itself, thereby delaying the shift operation of the circuit 1o.

As long as the flip-flop F6 is set when S7-“1'', the phase of the input clock φZN is the same as that of this circuit 1.
This is a state in which the bucket phase is ahead of the 00 phase (0 in Figure 4).
point). In this case, G10 is turned off at S7-+11'', and the set state of flip-flop F6 is not transmitted to the next flip-flop F1.
9 is turned on and the output Q of flip-flop F6 is “1”.
is inputted to the flip-flop F of the succeeding stage of Japanese Patent Application Laid-Open No. 2003-14223 (4) 2 via the gate G9FG1. First, a bypass loop is formed that bypasses the flip F1, and as a result, the shift operation of the circuit 10 is advanced by one period of the basic clock S6. With this process, the phase of the output clock φ011T follows the input clock φIN.

The flip 70 knob F5 is set when S7="1" in a state where the phase of the input clock φIN is ahead of the phase of the circuit 10, as described above. In this case, gate G7. By the action of G8,011, flip-flop Fe is bypassed and flip-flop F6
A bypass loop is formed connecting F1 and F1. Therefore, the shift operation of this circuit is accelerated, and the output clock φOU
The phase of T now follows the input clock φIN.

By the way, when S7-“1”, flip-flop F4
is set because the phase of the input clock φIN is out of phase with the phase of this circuit 10. In this case, it is assumed that noise or the like has occurred in the input clock φIN, and the operating phase of the circuit 10 is not manipulated and the current state is maintained. To that end, flip-flops F4 and F15 are directly connected.

By the above operation, an output clock φ0tlT whose phase is synchronized with the input clock φIH is obtained.

Effects of the Invention As explained in detail above, the digital PLL circuit according to the present invention performs basic clock frequency division processing, output clock phase manipulation processing, Since phase comparison processing between the input clock and the output clock is all performed, the entire circuit configuration becomes much simpler and smaller than the conventional one. However, since the basic clock circulation shift register circuit directly divides the frequency to generate the output clock, it is relatively easy to correspond to the input clock.

Further, in the present invention, the circuit having a counter structure with deep logic, which inhibits high-speed operation, is significantly reduced. Furthermore, since the operating characteristics of the cyclic shift register circuit can be easily set using a simple external gate circuit, it is possible to easily set the PLL operation according to the characteristics of the input clock.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional digital PLL circuit, FIG. 2 is a timing diagram thereof, and FIG. 3 is a block diagram of a digital PLL circuit according to an embodiment of the present invention. . φIN...Input clock, φOUT...
・Output clock, 6...Fixed oscillator, 7...
...Changing point detection circuit, 10... Circulating shift register circuit, F1 to F6, old... Flip 70 knobs, 0
1-011...Gate circuit. Name of agent: Patent attorney Toshio Nakao 1 person - ＾ ＾ ＋ C6 ＾ ＾ ＾ ＾

Claims (1)

[Claims] The base clock includes a change point detection circuit that detects a change point of the input clock, a fixed oscillator that generates a basic clock having a frequency that is an integral multiple of the basic frequency of the input clock, a plurality of flip-flops, and a plurality of gate circuits. and a cyclic shift register circuit in which specific signal bits are cyclically shifted in synchronization with the gate circuit, and the gate circuit is incorporated to control the shift destination of information between the flip-flops in response to the output of the change point detection circuit. In the cyclic shift register circuit, a loop for delaying the shift of the specific signal bit according to the relationship between the position of the specific signal bit and the output timing of the change point detection circuit and a predetermined 7 lip-flop are bypassed. A digital PLL circuit comprising: a loop for advancing the shift of the specific signal bit; and an output clock is taken out from a flip-flop in a predetermined stage of the cyclic shift register circuit.