JPS5773545A - Phase synchronizing system - Google Patents

Phase synchronizing system

Info

Publication number
JPS5773545A
JPS5773545A JP55148147A JP14814780A JPS5773545A JP S5773545 A JPS5773545 A JP S5773545A JP 55148147 A JP55148147 A JP 55148147A JP 14814780 A JP14814780 A JP 14814780A JP S5773545 A JPS5773545 A JP S5773545A
Authority
JP
Japan
Prior art keywords
signal
frequency
phase
counter
reference signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55148147A
Other languages
Japanese (ja)
Other versions
JPS6037665B2 (en
Inventor
Kuninosuke Ihira
Shigeyuki Umigami
Hiroya Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55148147A priority Critical patent/JPS6037665B2/en
Publication of JPS5773545A publication Critical patent/JPS5773545A/en
Publication of JPS6037665B2 publication Critical patent/JPS6037665B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To increase the accuracy of synchronism, by synchronizing the phase of a reference signal, such as a transmission element synchronizing signal and a picked up modulation speed component, with the phase of processing such as data fetch and demodulation digitally. CONSTITUTION:An output frequency of an oscillator 11 is a little higher than N times the frequency of reference signal. The output signal from the oscillator 11 is inputted to a counter 13 via an interleaving circuit 12. The counter 13 frequency- divides the input signal to input signal to 1/N. The frequency of the output signal of the counter 13 is compared with the frequency of the reference signal at the phase comparator 11. The phase difference signal as the result of comparison is fed back to the control input of the circuit 12. Thus, the phase synchronism between the output signal of the counter 13 and the reference signal is taken.
JP55148147A 1980-10-24 1980-10-24 Phase synchronization method Expired JPS6037665B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55148147A JPS6037665B2 (en) 1980-10-24 1980-10-24 Phase synchronization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55148147A JPS6037665B2 (en) 1980-10-24 1980-10-24 Phase synchronization method

Publications (2)

Publication Number Publication Date
JPS5773545A true JPS5773545A (en) 1982-05-08
JPS6037665B2 JPS6037665B2 (en) 1985-08-27

Family

ID=15446310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55148147A Expired JPS6037665B2 (en) 1980-10-24 1980-10-24 Phase synchronization method

Country Status (1)

Country Link
JP (1) JPS6037665B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142623A (en) * 1983-12-28 1985-07-27 Matsushita Graphic Commun Syst Inc Digital pll circuit
JPH01293039A (en) * 1988-05-20 1989-11-27 Nitsuko Corp Synchronizing system

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6330691A (en) * 1986-07-23 1988-02-09 堀井　清之 Flow-path changeable bent pipe
JPS6353961U (en) * 1986-09-29 1988-04-11

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142623A (en) * 1983-12-28 1985-07-27 Matsushita Graphic Commun Syst Inc Digital pll circuit
JPH0345935B2 (en) * 1983-12-28 1991-07-12 Matsushita Graphic Communic
JPH01293039A (en) * 1988-05-20 1989-11-27 Nitsuko Corp Synchronizing system

Also Published As

Publication number Publication date
JPS6037665B2 (en) 1985-08-27

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