JPS5651127A - Synchronizing circuit - Google Patents

Synchronizing circuit

Info

Publication number
JPS5651127A
JPS5651127A JP12731179A JP12731179A JPS5651127A JP S5651127 A JPS5651127 A JP S5651127A JP 12731179 A JP12731179 A JP 12731179A JP 12731179 A JP12731179 A JP 12731179A JP S5651127 A JPS5651127 A JP S5651127A
Authority
JP
Japan
Prior art keywords
oscillation
input
synchronizing circuit
output
frequency division
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12731179A
Other languages
Japanese (ja)
Inventor
Masao Kuribayashi
Original Assignee
Oki Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Ind Co Ltd filed Critical Oki Electric Ind Co Ltd
Priority to JP12731179A priority Critical patent/JPS5651127A/en
Publication of JPS5651127A publication Critical patent/JPS5651127A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation

Abstract

PURPOSE:To synchronize forcedly asynchronous operations of plural independent control systems having oscillation systems and frequency dividing stages with one another, by adding a synchronizing circuit. CONSTITUTION:The oscillation signal generated by oscillation system 18 is input to synchronizing circuit 16 from oscillation signal output 17, and meanwhile, the oscillation signal generated by 18 simultaneously is frequency-divided, and the output is input to the one side of the frequency division input of the synchronizing circuit from frequency division output 19. At this time, frequency division output 22 of oscillation system 21 has been input to another frequency division input of the synchronizing circuit, and the output of synchronizing circuit 16 has been input to oscillation signal input 20 of oscillation system 21. The frequency division result from both oscillation systems is input to synchronizing circuit 16, and by detecting their difference (phase difference), the oscillation signal input to oscillation system 21 is controlled to synchronize oscillation systems 18 and 21 with each other.
JP12731179A 1979-10-04 1979-10-04 Synchronizing circuit Pending JPS5651127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12731179A JPS5651127A (en) 1979-10-04 1979-10-04 Synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12731179A JPS5651127A (en) 1979-10-04 1979-10-04 Synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS5651127A true JPS5651127A (en) 1981-05-08

Family

ID=14956795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12731179A Pending JPS5651127A (en) 1979-10-04 1979-10-04 Synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS5651127A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0125768A2 (en) * 1983-04-29 1984-11-21 Tektronix, Inc. Method and apparatus for generating phase locked digital clock signals

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0125768A2 (en) * 1983-04-29 1984-11-21 Tektronix, Inc. Method and apparatus for generating phase locked digital clock signals

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